Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2019-12-22T13:53:39 |
PROP_intWbtProjectID=74DAB3A9CF394FAB880091651D533277 |
PROP_intWbtProjectIteration=4 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3A and Spartan3AN |
PROP_xilxBitgCfg_GenOpt_BinaryFile=true |
PROP_DevDevice=xc3s50a |
PROP_DevFamilyPMName=spartan3a |
PROP_DevPackage=tq144 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-5 |
PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
FILE_VHDL=7 |
FILE_XAW=1 |