Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s50a
Project ID (random number) ac81ae701e324762856def2fbeed7730.74DAB3A9CF394FAB880091651D533277.4 Target Package: tq144
Registration ID 211373645_0_0_435 Target Speed: -5
Date Generated 2019-12-22T15:50:55 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name AMD Phenom(tm) II X4 955 Processor CPU Speed 3616 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=14
  • 10-bit adder=5
  • 10-bit addsub=1
  • 10-bit subtractor=3
  • 2-bit subtractor=1
  • 3-bit subtractor=2
  • 4-bit adder=2
Comparators=37
  • 10-bit comparator greatequal=6
  • 10-bit comparator greater=6
  • 10-bit comparator less=5
  • 10-bit comparator lessequal=15
  • 4-bit comparator greatequal=1
  • 4-bit comparator lessequal=1
  • 5-bit comparator greatequal=1
  • 5-bit comparator lessequal=1
  • 6-bit comparator less=1
Counters=3
  • 10-bit up counter=2
  • 7-bit down counter=1
FSMs=1 Multiplexers=3
  • 1-bit 8-to-1 multiplexer=2
  • 7-bit 16-to-1 multiplexer=1
RAMs=1
  • 2048x8-bit single-port block RAM=1
ROMs=3
  • 16x7-bit ROM=1
  • 64x7-bit ROM=1
  • 8x8-bit ROM=1
Registers=66
  • Flip-Flops=66
MiscellaneousStatistics
  • AGG_BONDED_IO=9
  • AGG_IO=9
  • AGG_SLICE=247
  • NUM_4_INPUT_LUT=479
  • NUM_BONDED_IBUF=4
  • NUM_BONDED_IOB=5
  • NUM_BUFGMUX=2
  • NUM_CYMUX=150
  • NUM_DCM=1
  • NUM_LUT_RT=24
  • NUM_RAMB16BWE=1
  • NUM_SLICEL=247
  • NUM_SLICE_FF=81
  • NUM_XOR=78
NetStatistics
  • NumNets_Active=482
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=11
  • NumNodesOfType_Active_BRAMDUMMY=8
  • NumNodesOfType_Active_CLKPIN=56
  • NumNodesOfType_Active_CNTRLPIN=100
  • NumNodesOfType_Active_DOUBLE=827
  • NumNodesOfType_Active_DUMMY=1423
  • NumNodesOfType_Active_DUMMYBANK=13
  • NumNodesOfType_Active_DUMMYESC=5
  • NumNodesOfType_Active_GLOBAL=22
  • NumNodesOfType_Active_HFULLHEX=7
  • NumNodesOfType_Active_HLONG=1
  • NumNodesOfType_Active_HUNIHEX=33
  • NumNodesOfType_Active_INPUT=1565
  • NumNodesOfType_Active_IOBOUTPUT=4
  • NumNodesOfType_Active_OMUX=393
  • NumNodesOfType_Active_OUTPUT=477
  • NumNodesOfType_Active_PREBXBY=353
  • NumNodesOfType_Active_VFULLHEX=33
  • NumNodesOfType_Active_VLONG=9
  • NumNodesOfType_Active_VUNIHEX=42
  • NumNodesOfType_Vcc_BRAMDUMMY=5
  • NumNodesOfType_Vcc_CNTRLPIN=2
  • NumNodesOfType_Vcc_INPUT=18
  • NumNodesOfType_Vcc_PREBXBY=13
  • NumNodesOfType_Vcc_VCCOUT=18
SiteStatistics
  • IBUF-DIFFMLR=2
  • IBUF-DIFFMTB=1
  • IBUF-DIFFSI_NDT=1
  • IOB-DIFFMLR=1
  • IOB-DIFFSLR=4
  • SLICEL-SLICEM=106
SiteSummary
  • BUFGMUX=2
  • BUFGMUX_GCLKMUX=2
  • BUFGMUX_GCLK_BUFFER=2
  • DCM=1
  • DCM_DCM=1
  • IBUF=4
  • IBUF_DELAY_ADJ_BBOX=4
  • IBUF_INBUF=4
  • IBUF_PAD=4
  • IOB=5
  • IOB_OUTBUF=5
  • IOB_PAD=5
  • RAMB16BWE=1
  • RAMB16BWE_RAMB16BWE=1
  • SLICEL=247
  • SLICEL_C1VDD=14
  • SLICEL_C2VDD=12
  • SLICEL_CYMUXF=78
  • SLICEL_CYMUXG=72
  • SLICEL_F=241
  • SLICEL_F5MUX=34
  • SLICEL_F6MUX=8
  • SLICEL_FFX=45
  • SLICEL_FFY=36
  • SLICEL_G=238
  • SLICEL_GNDF=11
  • SLICEL_GNDG=8
  • SLICEL_XORF=40
  • SLICEL_XORG=38
 
Configuration Data
BUFGMUX
  • S=[S_INV:2] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:2]
  • S=[S_INV:2] [S:0]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[9:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:4]
  • IBUF_DELAY_VALUE=[DLY0:4]
  • IFD_DELAY_VALUE=[DLY0:4]
  • SEL_IN=[SEL_IN:4] [SEL_IN_INV:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:3] [LVCMOS33:1]
  • PULL=[PULLUP:3]
IOB
  • O1=[O1_INV:0] [O1:5]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:5]
  • SUSPEND=[3STATE:5]
IOB_PAD
  • DRIVEATTRBOX=[12:5]
  • IOATTRBOX=[LVCMOS33:5]
  • SLEW=[SLOW:5]
RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:0] [WEB0_INV:1]
  • WEB1=[WEB1:0] [WEB1_INV:1]
  • WEB2=[WEB2_INV:1] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:1]
RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • DATA_WIDTH_A=[9:1]
  • DATA_WIDTH_B=[0:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:0] [WEB0_INV:1]
  • WEB1=[WEB1:0] [WEB1_INV:1]
  • WEB2=[WEB2_INV:1] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:1]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
SLICEL
  • BX=[BX_INV:0] [BX:53]
  • BY=[BY:14] [BY_INV:1]
  • CE=[CE:46] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:64]
  • CLK=[CLK:53] [CLK_INV:0]
  • SR=[SR:0] [SR_INV:53]
SLICEL_CYMUXF
  • 0=[0:78] [0_INV:0]
  • 1=[1_INV:0] [1:78]
SLICEL_CYMUXG
  • 0=[0:72] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:34] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:8] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:39] [CE_INV:0]
  • CK=[CK:45] [CK_INV:0]
  • D=[D:45] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:40] [INIT1:5]
  • FFX_SR_ATTR=[SRLOW:40] [SRHIGH:5]
  • LATCH_OR_FF=[FF:45]
  • SR=[SR:0] [SR_INV:45]
  • SYNC_ATTR=[ASYNC:45]
SLICEL_FFY
  • CE=[CE:35] [CE_INV:0]
  • CK=[CK:36] [CK_INV:0]
  • D=[D:35] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:32] [INIT1:4]
  • FFY_SR_ATTR=[SRLOW:32] [SRHIGH:4]
  • LATCH_OR_FF=[FF:36]
  • SR=[SR:0] [SR_INV:36]
  • SYNC_ATTR=[ASYNC:36]
SLICEL_XORF
  • 1=[1_INV:0] [1:40]
 
Pin Data
BUFGMUX
  • I0=2
  • O=2
  • S=2
BUFGMUX_GCLKMUX
  • I0=2
  • OUT=2
  • S=2
BUFGMUX_GCLK_BUFFER
  • IN=2
  • OUT=2
DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
DCM_DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
IBUF
  • I=4
  • PAD=4
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=4
  • SEL_IN=4
IBUF_INBUF
  • IN=4
  • OUT=4
IBUF_PAD
  • PAD=4
IOB
  • O1=5
  • PAD=5
IOB_OUTBUF
  • IN=5
  • OUT=5
IOB_PAD
  • PAD=5
RAMB16BWE
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DOA0=1
  • DOA1=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • ENA=1
  • SSRA=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
RAMB16BWE_RAMB16BWE
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DOA0=1
  • DOA1=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • ENA=1
  • SSRA=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
SLICEL
  • BX=53
  • BY=15
  • CE=46
  • CIN=64
  • CLK=53
  • COUT=72
  • F1=238
  • F2=222
  • F3=146
  • F4=107
  • F5=16
  • FXINA=8
  • FXINB=8
  • G1=236
  • G2=220
  • G3=149
  • G4=99
  • SR=53
  • X=145
  • XQ=45
  • Y=141
  • YQ=36
SLICEL_C1VDD
  • 1=14
SLICEL_C2VDD
  • 1=12
SLICEL_CYMUXF
  • 0=78
  • 1=78
  • OUT=78
  • S0=78
SLICEL_CYMUXG
  • 0=72
  • 1=72
  • OUT=72
  • S0=72
SLICEL_F
  • A1=238
  • A2=222
  • A3=146
  • A4=107
  • D=241
SLICEL_F5MUX
  • F=33
  • G=34
  • OUT=34
  • S0=34
SLICEL_F6MUX
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
SLICEL_FFX
  • CE=39
  • CK=45
  • D=45
  • Q=45
  • SR=45
SLICEL_FFY
  • CE=35
  • CK=36
  • D=36
  • Q=36
  • SR=36
SLICEL_G
  • A1=236
  • A2=220
  • A3=149
  • A4=99
  • D=238
SLICEL_GNDF
  • 0=11
SLICEL_GNDG
  • 0=8
SLICEL_XORF
  • 0=40
  • 1=40
  • O=40
SLICEL_XORG
  • 0=38
  • 1=38
  • O=38
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-tq144-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s50a-tq144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-tq144-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s50a-tq144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-tq144-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s50a-tq144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-tq144-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s50a-tq144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 7 6 0 0 0 0 0
arwz 22 22 0 0 0 0 0
bitgen 12 12 0 0 0 0 0
map 53 46 0 0 0 0 0
ngcbuild 1 1 0 0 0 0 0
ngdbuild 74 74 0 0 0 0 0
par 49 46 3 0 0 0 0
trce 47 47 0 0 0 0 0
xst 100 100 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_c_tip_of_day.htm ( 1 ) /doc/usenglish/isehelp/pn_db_npw_create_new_project.htm ( 1 )
/doc/usenglish/wizards/arwz/awz_db_dcmgen.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2019-12-22T13:53:39
PROP_intWbtProjectID=74DAB3A9CF394FAB880091651D533277 PROP_intWbtProjectIteration=4
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_AutoTop=true
PROP_DevFamily=Spartan3A and Spartan3AN PROP_xilxBitgCfg_GenOpt_BinaryFile=true
PROP_DevDevice=xc3s50a PROP_DevFamilyPMName=spartan3a
PROP_DevPackage=tq144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=7
FILE_XAW=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=7 NGDBUILD_NUM_FDCE=65
NGDBUILD_NUM_FDPE=9 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=10 NGDBUILD_NUM_LUT1=26 NGDBUILD_NUM_LUT2=145 NGDBUILD_NUM_LUT2_D=1
NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=80 NGDBUILD_NUM_LUT3_D=5 NGDBUILD_NUM_LUT3_L=4
NGDBUILD_NUM_LUT4=171 NGDBUILD_NUM_LUT4_D=9 NGDBUILD_NUM_LUT4_L=25 NGDBUILD_NUM_MUXCY=152
NGDBUILD_NUM_MUXF5=33 NGDBUILD_NUM_MUXF6=8 NGDBUILD_NUM_OBUF=5 NGDBUILD_NUM_RAMB16BWE=1
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=80
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=7 NGDBUILD_NUM_FDCE=65
NGDBUILD_NUM_FDPE=9 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=10 NGDBUILD_NUM_LUT1=26 NGDBUILD_NUM_LUT2=145 NGDBUILD_NUM_LUT2_D=1
NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=80 NGDBUILD_NUM_LUT3_D=5 NGDBUILD_NUM_LUT3_L=4
NGDBUILD_NUM_LUT4=171 NGDBUILD_NUM_LUT4_D=9 NGDBUILD_NUM_LUT4_L=25 NGDBUILD_NUM_MUXCY=152
NGDBUILD_NUM_MUXF5=33 NGDBUILD_NUM_MUXF6=8 NGDBUILD_NUM_OBUF=5 NGDBUILD_NUM_PULLUP=3
NGDBUILD_NUM_RAMB16BWE=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=80
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s50a-5-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5