pong_top Project Status (12/22/2019 - 15:50:57)
Project File: PongText01.xise Parser Errors: No Errors
Module Name: pong_top Implementation State: Programming File Generated
Target Device: xc3s50a-5tq144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
23 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 81 1,408 5%  
Number of 4 input LUTs 455 1,408 32%  
Number of occupied Slices 247 704 35%  
    Number of Slices containing only related logic 247 247 100%  
    Number of Slices containing unrelated logic 0 247 0%  
Total Number of 4 input LUTs 479 1,408 34%  
    Number used as logic 455      
    Number used as a route-thru 24      
Number of bonded IOBs 9 108 8%  
Number of BUFGMUXs 2 24 8%  
Number of DCMs 1 2 50%  
Number of RAMB16BWEs 1 3 33%  
Average Fanout of Non-Clock Nets 3.66      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentniedz. 22. gru 15:50:07 201907 Warnings (0 new)5 Infos (0 new)
Translation ReportCurrentniedz. 22. gru 15:50:12 2019001 Info (0 new)
Map ReportCurrentniedz. 22. gru 15:50:17 201908 Warnings (0 new)4 Infos (0 new)
Place and Route ReportCurrentniedz. 22. gru 15:50:26 2019000
Power Report     
Post-PAR Static Timing ReportCurrentniedz. 22. gru 15:50:31 2019005 Infos (0 new)
Bitgen ReportCurrentniedz. 22. gru 15:50:54 201908 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentniedz. 22. gru 15:50:55 2019
WebTalk Log FileCurrentniedz. 22. gru 15:50:56 2019

Date Generated: 12/22/2019 - 15:50:57