PnR Messages

Report Title PnR Report
Design File D:\_FPGA_Proj\GOWIN\HyperRAM\project\impl\gwsynthesis\hpram.vg
Physical Constraints File D:\_FPGA_Proj\GOWIN\HyperRAM\project\src\hpram.cst
Timing Constraints File D:\_FPGA_Proj\GOWIN\HyperRAM\project\src\hpram.sdc
Version V1.9.8.03
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Mon May 09 16:08:05 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.215s, Elapsed time = 0h 0m 0.216s Placement Phase 1: CPU time = 0h 0m 0.157s, Elapsed time = 0h 0m 0.157s Placement Phase 2: CPU time = 0h 0m 0.434s, Elapsed time = 0h 0m 0.434s Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.192s, Elapsed time = 0h 0m 0.192s Routing Phase 2: CPU time = 0h 0m 0.835s, Elapsed time = 0h 0m 0.834s Total Routing: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 145MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1003/4608 21%
    --LUT,ALU,ROM16 1003(861 LUT, 142 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 646/3609 17%
    --Logic Register as Latch 0/3456 0%
    --Logic Register as FF 645/3456 18%
    --I/O Register as Latch 0/153 0%
    --I/O Register as FF 1/153 1%
CLS 648/2304 28%
I/O Port 4 -
I/O Buf 4 -
    --Input Buf 2 -
    --Output Buf 2 -
    --Inout Buf 0 -
IOLOGIC 8 IDES4
12 OSER4
10 IODELAY
37%
BSRAM 1 SDPX9B
10%
DSP 00%
PLL 1/2 50%
DCS 0/4 0%
DQCE 0/12 0%
OSC 0/1 0%
CLKDIV 1/6 16%
DLLDLY 0/6 0%
DHCEN 1/12 8%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 1/10(10%)
bank 1 0/10(0%)
bank 2 0/9(0%)
bank 3 3/24(12%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 2/8(25%)
SECONDARY 2/8(25%)
GCLK_PIN 1/5(20%)
PLL 1/2(50%)
CLKDIV 1/6(16%)
DLLDLY 0/6(0%)

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY LEFT RIGHT
clk_x1 PRIMARY LEFT RIGHT
rst_n_i SECONDARY -
ddr_rsti SECONDARY -
memory_clk HCLK TOP[1] BOTTOM[1]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor BankVccio
clk 22/3 Y in IOB22[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
rst_n 15/3 Y in IOB5[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
init_calib 13/3 Y out IOB4[A] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.8
error 10/0 Y out IOT7[A] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
4/0 - out IOT2[B] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.8
6/0 - in IOT3[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
7/0 - in IOT3[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
8/0 - in IOT4[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
9/0 - in IOT5[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
10/0 error out IOT7[A] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.8
1/0 - in IOT10[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
2/0 - in IOT10[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
48/1 - in IOT11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
47/1 - in IOT11[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
45/1 - in IOT13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
46/1 - in IOT13[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
43/1 - in IOT17[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
44/1 - in IOT17[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
41/1 - in IOT20[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
42/1 - in IOT20[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
39/1 - in IOT26[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
40/1 - in IOT26[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
13/3 init_calib out IOB4[A] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.8
14/3 - in IOB4[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
15/3 rst_n in IOB5[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
16/3 - in IOB6[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
17/3 - in IOB6[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
18/3 - in IOB13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
19/3 - in IOB13[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
20/3 - in IOB16[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
21/3 - in IOB16[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
22/3 clk in IOB22[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
23/3 - in IOB22[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
35/2 - in IOR2[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
34/2 - in IOR2[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
33/2 - in IOR9[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
32/2 - in IOR11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
31/2 - in IOR11[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
30/2 - in IOR15[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
29/2 - in IOR15[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
28/2 - in IOR17[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
27/2 - in IOR17[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -