Report Title |
Power Analysis Report |
Design File |
D:\_FPGA_Proj\GOWIN\HyperRAM\project\impl\gwsynthesis\hpram.vg |
Physical Constraints File |
D:\_FPGA_Proj\GOWIN\HyperRAM\project\src\hpram.cst |
Timing Constraints File |
D:\_FPGA_Proj\GOWIN\HyperRAM\project\src\hpram.sdc |
Version |
V1.9.8.03 |
Part Number |
GW1NSR-LV4CQN48PC7/I6 |
Device |
GW1NSR-4C |
Created Time |
Mon May 09 16:08:05 2022
|
Legal Announcement |
Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved. |
Total Power (mW) |
32.666 |
Quiescent Power (mW) |
8.738 |
Dynamic Power (mW) |
23.928 |
Junction Temperature |
26.333 |
Theta JA |
40.580 |
Max Allowed Ambient Temperature |
83.667 |
Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
Use Vectorless Estimation |
false |
Filter Glitches |
false |
Related Vcd File |
|
Related Saif File |
|
Use Custom Theta JA |
false |
Air Flow |
LFM_0 |
Heat Sink |
None |
Use Custom Theta SA |
false |
Board Thermal Model |
None |
Use Custom Theta JB |
false |
Ambient Temperature |
25.000
|
Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
VCC |
1.200 |
18.635 |
2.045 |
24.816 |
VCCX |
2.500 |
0.365 |
2.424 |
6.973 |
VCCO18 |
1.800 |
0.363 |
0.124 |
0.877 |
Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
Logic |
0.532 |
NA |
12.297 |
IO |
2.728
| 0.687
| 24.663
|
BSRAM |
4.368
| NA |
NA |
PLL |
4.686
| NA |
NA |
DLL |
12.288
| NA |
NA |
Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
hpram_syn_top |
21.874 |
21.874(17.188) |
hpram_syn_top/u_hpram_top/ |
17.055 |
17.055(17.055) |
hpram_syn_top/u_hpram_top/u_hpram_top_0/ |
17.055 |
17.055(4.750) |
hpram_syn_top/u_hpram_top/u_hpram_top_0/u_hpram_init/ |
0.194 |
0.194(0.000) |
hpram_syn_top/u_hpram_top/u_hpram_top_0/u_hpram_sync/ |
0.039 |
0.039(0.000) |
hpram_syn_top/u_hpram_top/u_hpram_top_0/u_hpram_wd/ |
4.517 |
4.517(4.464) |
hpram_syn_top/u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/ |
4.464 |
4.464(0.000) |
hpram_syn_top/u_test/ |
0.133 |
0.133(0.000) |
Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
clk_x1 |
100.000 |
4.831 |
NO CLOCK DOMAIN |
0.000 |
0.000 |
clk |
70.000 |
4.727 |
clk_x2 |
200.000 |
12.329 |