#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020
#install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-032

# Tue Aug  4 16:22:01 2020

#Implementation: rev_1


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\generic\gw1ns.v" (library work)
@I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v":"E:\IP_verify\1.9.6.0.1\IP_web\psram_hpram_ref_design\Hpram\project\src\hyperram_memory_interface\temp\HYPERRAM\hpram_define.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v":"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\hpram_local_define.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v":"E:\IP_verify\1.9.6.0.1\IP_web\psram_hpram_ref_design\Hpram\project\src\hyperram_memory_interface\temp\HYPERRAM\hpram_param.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v":"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\hpram_local_param.v" (library work)
@I::"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\hpram_code_166.v" (library work)
@N:CG346 : hpram_code_166.v(1786) | Read full_case directive.
@N:CG347 : hpram_code_166.v(1786) | Read a parallel_case directive.
@W:CG286 : hpram_code_166.v(1786) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive.
Verilog syntax check successful!
Selecting top level module HyperRAM_Memory_Interface_Top
Running optimization stage 1 on IODELAY .......
Running optimization stage 1 on OBUF .......
Running optimization stage 1 on OSER4 .......
Running optimization stage 1 on IDES4 .......
Running optimization stage 1 on \~hpram_lane.HyperRAM_Memory_Interface_Top _Z1 .......
Running optimization stage 1 on IOBUF .......
Running optimization stage 1 on \~hpram_wd.HyperRAM_Memory_Interface_Top  .......
Running optimization stage 1 on \~hpram_init.HyperRAM_Memory_Interface_Top  .......
Running optimization stage 1 on \~hpram_sync.HyperRAM_Memory_Interface_Top  .......
Running optimization stage 1 on DLL .......
Running optimization stage 1 on DHCEN .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on \~hpram_top.HyperRAM_Memory_Interface_Top  .......
@N:CG364 : HPRAM_TOP.v(5) | Synthesizing module HyperRAM_Memory_Interface_Top in library work.
Running optimization stage 1 on HyperRAM_Memory_Interface_Top .......
Running optimization stage 2 on HyperRAM_Memory_Interface_Top .......
Running optimization stage 2 on \~hpram_top.HyperRAM_Memory_Interface_Top  .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on DHCEN .......
Running optimization stage 2 on DLL .......
Running optimization stage 2 on \~hpram_sync.HyperRAM_Memory_Interface_Top  .......
Extracted state machine for register flag
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Running optimization stage 2 on \~hpram_init.HyperRAM_Memory_Interface_Top  .......
Extracted state machine for register c_state
State machine has 11 reachable states with original encodings of:
   00000000001
   00000000010
   00000000100
   00000001000
   00000010000
   00000100000
   00001000000
   00010000000
   00100000000
   01000000000
   10000000000
Running optimization stage 2 on IOBUF .......
Running optimization stage 2 on IDES4 .......
Running optimization stage 2 on \~hpram_lane.HyperRAM_Memory_Interface_Top _Z1 .......
Running optimization stage 2 on OSER4 .......
Running optimization stage 2 on \~hpram_wd.HyperRAM_Memory_Interface_Top  .......
Running optimization stage 2 on OBUF .......
Running optimization stage 2 on IODELAY .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 100MB peak: 102MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  4 16:22:04 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
@N:NF107 : hpram_top.v(5) | Selected library: work cell: HyperRAM_Memory_Interface_Top view verilog as top level
@N:NF107 : hpram_top.v(5) | Selected library: work cell: HyperRAM_Memory_Interface_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  4 16:22:05 2020

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  hyperram_memory_interface_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 22MB peak: 22MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  4 16:22:05 2020

###########################################################]


###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
@N:NF107 : hpram_top.v(5) | Selected library: work cell: HyperRAM_Memory_Interface_Top view verilog as top level
@N:NF107 : hpram_top.v(5) | Selected library: work cell: HyperRAM_Memory_Interface_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 93MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  4 16:22:06 2020

###########################################################]


Premap Report



# Tue Aug  4 16:22:07 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A:MF827 :  | No constraint file specified. 
Linked File:  hyperram_memory_interface_scck.rpt
See clock summary report "E:\IP_verify\1.9.6.0.1\IP_web\psram_hpram_ref_design\Hpram\project\src\hyperram_memory_interface\temp\HYPERRAM\rev_1\hyperram_memory_interface_scck.rpt"
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 131MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)



Clock Summary
******************

          Start                                                                                        Requested     Requested     Clock                                                                                Clock                     Clock
Level     Clock                                                                                        Frequency     Period        Type                                                                                 Group                     Load 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                                                                       100.0 MHz     10.000        system                                                                               system_clkgroup           0    
                                                                                                                                                                                                                                                       
0 -       _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock                            150.8 MHz     6.630         inferred                                                                             Autoconstr_clkgroup_0     606  
1 .         _~hpram_init_HyperRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0]     150.8 MHz     6.630         derived (from _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock)     Autoconstr_clkgroup_0     8    
1 .         _~hpram_wd_HyperRAM_Memory_Interface_Top_|step_derived_clock[0]                            150.8 MHz     6.630         derived (from _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock)     Autoconstr_clkgroup_0     2    
                                                                                                                                                                                                                                                       
0 -       HyperRAM_Memory_Interface_Top|clk                                                            206.8 MHz     4.836         inferred                                                                             Autoconstr_clkgroup_1     32   
                                                                                                                                                                                                                                                       
0 -       _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_x2p_inferred_clock                            100.0 MHz     10.000        inferred                                                                             Autoconstr_clkgroup_2     20   
=======================================================================================================================================================================================================================================================



Clock Load Summary
***********************

                                                                                           Clock     Source                                                                   Clock Pin                                                                    Non-clock Pin                                                                              Non-clock Pin
Clock                                                                                      Load      Pin                                                                      Seq Example                                                                  Seq Example                                                                                Comb Example 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                                                     0         -                                                                        -                                                                            -                                                                                          -            
                                                                                                                                                                                                                                                                                                                                                                   
_~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock                          606       u_hpram_top.clkdiv.CLKOUT(CLKDIV)                                        u_hpram_top.rd_data_valid_d.C                                                u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.iserdes_gen\[7\]\.u_ides4.PCLK     -            
_~hpram_init_HyperRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0]     8         u_hpram_top.u_hpram_init.read_calibration\[0\]\.VALUE[0].Q[0](dffre)     u_hpram_top.u_hpram_wd.dq_iodelay_gen0\[0\]\.genblk1\[5\]\.iodelay.VALUE     -                                                                                          -            
_~hpram_wd_HyperRAM_Memory_Interface_Top_|step_derived_clock[0]                            2         u_hpram_top.u_hpram_wd.step[8:0].Q[0](dffr)                              u_hpram_top.u_hpram_wd.iodelayn0.VALUE                                       -                                                                                          -            
                                                                                                                                                                                                                                                                                                                                                                   
HyperRAM_Memory_Interface_Top|clk                                                          32        clk(port)                                                                u_hpram_top.u_hpram_sync.dll_rst.C                                           -                                                                                          -            
                                                                                                                                                                                                                                                                                                                                                                   
_~hpram_top_HyperRAM_Memory_Interface_Top_|clk_x2p_inferred_clock                          20        u_hpram_top.u_dqce_clk_x2p.CLKOUT(DHCEN)                                 u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mask_oser4.FCLK      -                                                                                          -            
===================================================================================================================================================================================================================================================================================================================================================================


@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\IP_verify\1.9.6.0.1\IP_web\psram_hpram_ref_design\Hpram\project\src\hyperram_memory_interface\temp\HYPERRAM\rev_1\hyperram_memory_interface.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 226MB peak: 226MB)

Encoding state machine c_state[10:0] (in view: work.\\\~hpram_init\.HyperRAM_Memory_Interface_Top\ (verilog))
original code -> new code
   00000000001 -> 00000000001
   00000000010 -> 00000000010
   00000000100 -> 00000000100
   00000001000 -> 00000001000
   00000010000 -> 00000010000
   00000100000 -> 00000100000
   00001000000 -> 00001000000
   00010000000 -> 00010000000
   00100000000 -> 00100000000
   01000000000 -> 01000000000
   10000000000 -> 10000000000
Encoding state machine flag[2:0] (in view: work.\\\~hpram_sync\.HyperRAM_Memory_Interface_Top\ (verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 229MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Aug  4 16:22:10 2020

###########################################################]


Map & Optimize Report



# Tue Aug  4 16:22:10 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

@N:MO111 :  | Tristate driver recalib_d_t[0] (in view: work.\\\~hpram_wd\.HyperRAM_Memory_Interface_Top\ (verilog)) on net recalib_d[0] (in view: work.\\\~hpram_wd\.HyperRAM_Memory_Interface_Top\ (verilog)) has its enable tied to GND. 

Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

Encoding state machine c_state[10:0] (in view: work.\\\~hpram_init\.HyperRAM_Memory_Interface_Top\ (verilog))
original code -> new code
   00000000001 -> 00000000001
   00000000010 -> 00000000010
   00000000100 -> 00000000100
   00000001000 -> 00000001000
   00000010000 -> 00000010000
   00000100000 -> 00000100000
   00001000000 -> 00001000000
   00010000000 -> 00010000000
   00100000000 -> 00100000000
   01000000000 -> 01000000000
   10000000000 -> 10000000000
Encoding state machine flag[2:0] (in view: work.\\\~hpram_sync\.HyperRAM_Memory_Interface_Top\ (verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 229MB peak: 229MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 231MB peak: 231MB)


Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 232MB peak: 232MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 232MB peak: 232MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 232MB peak: 232MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 233MB peak: 233MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 233MB peak: 233MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 233MB peak: 233MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 233MB peak: 233MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 237MB peak: 237MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		    -2.94ns		 608 /       405
   2		0h:00m:02s		    -2.94ns		 609 /       405
   3		0h:00m:02s		    -2.94ns		 609 /       405
Timing driven replication report
Added 6 Registers via timing driven replication
Added 3 LUTs via timing driven replication

   4		0h:00m:03s		    -1.82ns		 618 /       411
   5		0h:00m:03s		    -2.08ns		 617 /       411
   6		0h:00m:03s		    -2.08ns		 618 /       411
   7		0h:00m:03s		    -1.82ns		 618 /       411
   8		0h:00m:03s		    -1.82ns		 619 /       411
Timing driven replication report
Added 2 Registers via timing driven replication
Added 2 LUTs via timing driven replication


   9		0h:00m:03s		    -1.82ns		 620 /       413
  10		0h:00m:03s		    -1.57ns		 621 /       413
  11		0h:00m:03s		    -2.08ns		 621 /       413
  12		0h:00m:03s		    -2.08ns		 621 /       413
  13		0h:00m:03s		    -2.08ns		 621 /       413
  14		0h:00m:03s		    -2.08ns		 621 /       413

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 238MB peak: 239MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@W:MT453 :  | clock period is too long for clock _~hpram_wd_HyperRAM_Memory_Interface_Top_|step_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock _~hpram_init_HyperRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 239MB peak: 239MB)

@N:MF578 :  | Incompatible asynchronous control logic preventing generated clock conversion. 


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 33 clock pin(s) of sequential element(s)
4 gated/generated clock tree(s) driving 424 clock pin(s) of sequential element(s)
0 instances converted, 424 sequential instances remain driven by gated/generated clocks

======================================= Non-Gated/Non-Generated Clocks =======================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                       
--------------------------------------------------------------------------------------------------------------
ClockId0005        clk                 port                   33         u_hpram_top.u_hpram_sync.cs_memsync[0]
==============================================================================================================
======================================================================================================================================= Gated/Generated Clocks =======================================================================================================================================
Clock Tree ID     Driving Element                                              Drive Element Type     Fanout     Sample Instance                                                        Explanation                                                                                                   
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        u_hpram_top.clkdiv                                           CLKDIV                 394        u_hpram_top.rd_data_valid_d                                            Illegal instance on clock path. See the Gated Clocks description in the user guide for conversion requirements
ClockId0002        u_hpram_top.u_dqce_clk_x2p                                   DHCEN                  20         u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mask_oser4     No gated clock conversion method for cell cell:GOWIN.OSER4                                                    
ClockId0003        u_hpram_top.u_hpram_init.read_calibration\[0\]\.VALUE[0]     DFFCE                  8          u_hpram_top.u_hpram_wd.dq_iodelay_gen0\[0\]\.genblk1\[5\]\.iodelay     No gated clock conversion method for cell cell:GOWIN.IODELAY                                                  
ClockId0004        u_hpram_top.u_hpram_wd.step[0]                               DFFC                   2          u_hpram_top.u_hpram_wd.ck_delay\[0\]\.iodelay                          No gated clock conversion method for cell cell:GOWIN.IODELAY                                                  
======================================================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 164MB peak: 239MB)

Writing Analyst data base E:\IP_verify\1.9.6.0.1\IP_web\psram_hpram_ref_design\Hpram\project\src\hyperram_memory_interface\temp\HYPERRAM\rev_1\synwork\hyperram_memory_interface_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 240MB peak: 240MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 240MB peak: 240MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 240MB peak: 240MB)


Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 237MB peak: 241MB)

@W:MT246 : hpram_code_166.v(2181) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : hpram_code_166.v(2173) | Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : hpram_code_166.v(2161) | Blackbox DLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 :  | Found inferred clock _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock with period 7.93ns. Please declare a user-defined clock on net u_hpram_top.clk_out. 
@W:MT420 :  | Found inferred clock HyperRAM_Memory_Interface_Top|clk with period 6.34ns. Please declare a user-defined clock on port clk. 
@W:MT420 :  | Found inferred clock _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_x2p_inferred_clock with period 10.00ns. Please declare a user-defined clock on net u_hpram_top.clk_x2p. 
@N:MT615 :  | Found clock _~hpram_wd_HyperRAM_Memory_Interface_Top_|step_derived_clock[0] with period 15861.85ns  
@N:MT615 :  | Found clock _~hpram_init_HyperRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0] with period 15861.85ns  


##### START OF TIMING REPORT #####[
# Timing report written on Tue Aug  4 16:22:17 2020
#


Top view:               HyperRAM_Memory_Interface_Top
Requested Frequency:    0.1 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.400

                                                                                           Requested     Estimated     Requested     Estimated                Clock                                                                                Clock                
Starting Clock                                                                             Frequency     Frequency     Period        Period        Slack      Type                                                                                 Group                
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
HyperRAM_Memory_Interface_Top|clk                                                          157.6 MHz     134.0 MHz     6.345         7.464         -1.120     inferred                                                                             Autoconstr_clkgroup_1
_~hpram_init_HyperRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0]     0.1 MHz       NA            15861.850     NA            NA         derived (from _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock)     Autoconstr_clkgroup_0
_~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock                          126.1 MHz     107.2 MHz     7.931         9.331         -1.400     inferred                                                                             Autoconstr_clkgroup_0
_~hpram_top_HyperRAM_Memory_Interface_Top_|clk_x2p_inferred_clock                          100.0 MHz     NA            10.000        NA            NA         inferred                                                                             Autoconstr_clkgroup_2
_~hpram_wd_HyperRAM_Memory_Interface_Top_|step_derived_clock[0]                            0.1 MHz       NA            15861.850     NA            NA         derived (from _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock)     Autoconstr_clkgroup_0
System                                                                                     100.0 MHz     93.1 MHz      10.000        10.740        -0.740     system                                                                               system_clkgroup      
========================================================================================================================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                                                                                                |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                           Ending                                                             |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                             _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock  |  7.931       -0.740  |  No paths    -      |  No paths    -      |  No paths    -    
System                                                             HyperRAM_Memory_Interface_Top|clk                                  |  6.345       4.159   |  No paths    -      |  No paths    -      |  No paths    -    
_~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock  _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock  |  7.931       -1.400  |  No paths    -      |  No paths    -      |  No paths    -    
_~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock  _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_x2p_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
HyperRAM_Memory_Interface_Top|clk                                  System                                                             |  6.345       2.837   |  No paths    -      |  No paths    -      |  No paths    -    
HyperRAM_Memory_Interface_Top|clk                                  _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
HyperRAM_Memory_Interface_Top|clk                                  HyperRAM_Memory_Interface_Top|clk                                  |  6.345       -1.120  |  No paths    -      |  No paths    -      |  No paths    -    
=============================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: HyperRAM_Memory_Interface_Top|clk
====================================



Starting Points with Worst Slack
********************************

                                                Starting                                                                       Arrival           
Instance                                        Reference                             Type      Pin     Net                    Time        Slack 
                                                Clock                                                                                            
-------------------------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_sync.cs_memsync_fast[3]     HyperRAM_Memory_Interface_Top|clk     DFFCE     Q       cs_memsync_fast[3]     0.367       -1.120
u_hpram_top.u_hpram_sync.cs_memsync[4]          HyperRAM_Memory_Interface_Top|clk     DFFCE     Q       stop                   0.367       -1.113
u_hpram_top.u_hpram_sync.lock_cnt[0]            HyperRAM_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[0]            0.367       -0.636
u_hpram_top.u_hpram_sync.lock_syn[1]            HyperRAM_Memory_Interface_Top|clk     DFFC      Q       lock_cnt               0.367       -0.630
u_hpram_top.u_hpram_sync.lock_cnt[1]            HyperRAM_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[1]            0.367       -0.580
u_hpram_top.u_hpram_sync.lock_cnt[2]            HyperRAM_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[2]            0.367       -0.522
u_hpram_top.u_hpram_sync.lock_cnt[3]            HyperRAM_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[3]            0.367       -0.466
u_hpram_top.u_hpram_sync.cs_memsync[3]          HyperRAM_Memory_Interface_Top|clk     DFFCE     Q       cs_memsync[3]          0.367       -0.448
u_hpram_top.u_hpram_sync.lock_cnt[4]            HyperRAM_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[4]            0.367       -0.408
u_hpram_top.u_hpram_sync.lock_cnt[5]            HyperRAM_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[5]            0.367       -0.351
=================================================================================================================================================


Ending Points with Worst Slack
******************************

                                          Starting                                                                   Required           
Instance                                  Reference                             Type      Pin     Net                Time         Slack 
                                          Clock                                                                                         
----------------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_sync.flag[1]          HyperRAM_Memory_Interface_Top|clk     DFFC      D       flag_ns[1]         6.212        -1.120
u_hpram_top.u_hpram_sync.lock_cnt[15]     HyperRAM_Memory_Interface_Top|clk     DFFCE     D       lock_cnt_s[15]     6.212        -0.636
u_hpram_top.u_hpram_sync.lock_cnt[14]     HyperRAM_Memory_Interface_Top|clk     DFFCE     D       lock_cnt_s[14]     6.212        -0.580
u_hpram_top.u_hpram_sync.lock_cnt[13]     HyperRAM_Memory_Interface_Top|clk     DFFCE     D       lock_cnt_s[13]     6.212        -0.522
u_hpram_top.u_hpram_sync.lock_cnt[12]     HyperRAM_Memory_Interface_Top|clk     DFFCE     D       lock_cnt_s[12]     6.212        -0.466
u_hpram_top.u_hpram_sync.count[2]         HyperRAM_Memory_Interface_Top|clk     DFFC      D       N_21_i             6.212        -0.448
u_hpram_top.u_hpram_sync.lock_cnt[11]     HyperRAM_Memory_Interface_Top|clk     DFFCE     D       lock_cnt_s[11]     6.212        -0.408
u_hpram_top.u_hpram_sync.count[0]         HyperRAM_Memory_Interface_Top|clk     DFFC      D       N_25_i             6.212        -0.381
u_hpram_top.u_hpram_sync.lock_cnt[10]     HyperRAM_Memory_Interface_Top|clk     DFFCE     D       lock_cnt_s[10]     6.212        -0.351
u_hpram_top.u_hpram_sync.lock_cnt[9]      HyperRAM_Memory_Interface_Top|clk     DFFCE     D       lock_cnt_s[9]      6.212        -0.294
========================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.212

    - Propagation time:                      7.331
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.120

    Number of logic level(s):                4
    Starting point:                          u_hpram_top.u_hpram_sync.cs_memsync_fast[3] / Q
    Ending point:                            u_hpram_top.u_hpram_sync.flag[1] / D
    The start point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK
    The end   point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                                Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_sync.cs_memsync_fast[3]                         DFFCE     Q        Out     0.367     0.367 r     -         
cs_memsync_fast[3]                                                  Net       -        -       1.021     -           4         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1_N_3L3_N_2L1_0     LUT2      I1       In      -         1.388 r     -         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1_N_3L3_N_2L1_0     LUT2      F        Out     1.099     2.487 f     -         
m26_0_N_2L1_N_3L3_N_2L1_0                                           Net       -        -       0.766     -           1         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1_N_3L3             LUT4      I2       In      -         3.253 f     -         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1_N_3L3             LUT4      F        Out     0.822     4.075 f     -         
m26_0_N_2L1_1                                                       Net       -        -       0.766     -           1         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1                   LUT4      I3       In      -         4.840 f     -         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1                   LUT4      F        Out     0.626     5.466 f     -         
m26_0_N_2L1                                                         Net       -        -       0.766     -           1         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0                         LUT4      I1       In      -         6.232 f     -         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0                         LUT4      F        Out     1.099     7.331 f     -         
flag_ns[1]                                                          Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.flag[1]                                    DFFC      D        In      -         7.331 f     -         
===============================================================================================================================
Total path delay (propagation time + setup) of 7.464 is 4.146(55.5%) logic and 3.318(44.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.212

    - Propagation time:                      7.325
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.114

    Number of logic level(s):                4
    Starting point:                          u_hpram_top.u_hpram_sync.cs_memsync[4] / Q
    Ending point:                            u_hpram_top.u_hpram_sync.flag[1] / D
    The start point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK
    The end   point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                                Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_sync.cs_memsync[4]                              DFFCE     Q        Out     0.367     0.367 r     -         
stop                                                                Net       -        -       1.082     -           11        
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1_N_3L3_N_2L1_0     LUT2      I0       In      -         1.449 r     -         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1_N_3L3_N_2L1_0     LUT2      F        Out     1.032     2.481 f     -         
m26_0_N_2L1_N_3L3_N_2L1_0                                           Net       -        -       0.766     -           1         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1_N_3L3             LUT4      I2       In      -         3.247 f     -         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1_N_3L3             LUT4      F        Out     0.822     4.069 f     -         
m26_0_N_2L1_1                                                       Net       -        -       0.766     -           1         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1                   LUT4      I3       In      -         4.834 f     -         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0_N_2L1                   LUT4      F        Out     0.626     5.460 f     -         
m26_0_N_2L1                                                         Net       -        -       0.766     -           1         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0                         LUT4      I1       In      -         6.226 f     -         
u_hpram_top.u_hpram_sync.flag_ns_1_0_.m26_0                         LUT4      F        Out     1.099     7.325 f     -         
flag_ns[1]                                                          Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.flag[1]                                    DFFC      D        In      -         7.325 f     -         
===============================================================================================================================
Total path delay (propagation time + setup) of 7.458 is 4.079(54.7%) logic and 3.379(45.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.212

    - Propagation time:                      6.848
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.636

    Number of logic level(s):                17
    Starting point:                          u_hpram_top.u_hpram_sync.lock_cnt[0] / Q
    Ending point:                            u_hpram_top.u_hpram_sync.lock_cnt[15] / D
    The start point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK
    The end   point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_sync.lock_cnt[0]              DFFCE     Q        Out     0.367     0.367 r     -         
lock_cnt[0]                                       Net       -        -       1.021     -           2         
u_hpram_top.u_hpram_sync.lock_cnt_qxu_lofx[0]     LUT2      I1       In      -         1.388 r     -         
u_hpram_top.u_hpram_sync.lock_cnt_qxu_lofx[0]     LUT2      F        Out     1.099     2.487 f     -         
lock_cnt_qxu_lofx[0]                              Net       -        -       1.021     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[0]        ALU       I0       In      -         3.508 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[0]        ALU       COUT     Out     0.958     4.466 f     -         
lock_cnt_cry[0]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[1]        ALU       CIN      In      -         4.466 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[1]        ALU       COUT     Out     0.057     4.523 f     -         
lock_cnt_cry[1]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[2]        ALU       CIN      In      -         4.523 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[2]        ALU       COUT     Out     0.057     4.580 f     -         
lock_cnt_cry[2]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[3]        ALU       CIN      In      -         4.580 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[3]        ALU       COUT     Out     0.057     4.637 f     -         
lock_cnt_cry[3]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[4]        ALU       CIN      In      -         4.637 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[4]        ALU       COUT     Out     0.057     4.694 f     -         
lock_cnt_cry[4]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[5]        ALU       CIN      In      -         4.694 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[5]        ALU       COUT     Out     0.057     4.751 f     -         
lock_cnt_cry[5]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[6]        ALU       CIN      In      -         4.751 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[6]        ALU       COUT     Out     0.057     4.808 f     -         
lock_cnt_cry[6]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[7]        ALU       CIN      In      -         4.808 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[7]        ALU       COUT     Out     0.057     4.865 f     -         
lock_cnt_cry[7]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[8]        ALU       CIN      In      -         4.865 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[8]        ALU       COUT     Out     0.057     4.922 f     -         
lock_cnt_cry[8]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[9]        ALU       CIN      In      -         4.922 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[9]        ALU       COUT     Out     0.057     4.979 f     -         
lock_cnt_cry[9]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[10]       ALU       CIN      In      -         4.979 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[10]       ALU       COUT     Out     0.057     5.036 f     -         
lock_cnt_cry[10]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[11]       ALU       CIN      In      -         5.036 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[11]       ALU       COUT     Out     0.057     5.093 f     -         
lock_cnt_cry[11]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[12]       ALU       CIN      In      -         5.093 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[12]       ALU       COUT     Out     0.057     5.150 f     -         
lock_cnt_cry[12]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[13]       ALU       CIN      In      -         5.150 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[13]       ALU       COUT     Out     0.057     5.207 f     -         
lock_cnt_cry[13]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[14]       ALU       CIN      In      -         5.207 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[14]       ALU       COUT     Out     0.057     5.264 f     -         
lock_cnt_cry[14]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_s_0[15]         ALU       CIN      In      -         5.264 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_s_0[15]         ALU       SUM      Out     0.563     5.827 f     -         
lock_cnt_s[15]                                    Net       -        -       1.021     -           1         
u_hpram_top.u_hpram_sync.lock_cnt[15]             DFFCE     D        In      -         6.848 f     -         
=============================================================================================================
Total path delay (propagation time + setup) of 6.981 is 3.918(56.1%) logic and 3.063(43.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.212

    - Propagation time:                      6.842
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.630

    Number of logic level(s):                17
    Starting point:                          u_hpram_top.u_hpram_sync.lock_syn[1] / Q
    Ending point:                            u_hpram_top.u_hpram_sync.lock_cnt[15] / D
    The start point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK
    The end   point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_sync.lock_syn[1]              DFFC      Q        Out     0.367     0.367 r     -         
lock_cnt                                          Net       -        -       1.082     -           18        
u_hpram_top.u_hpram_sync.lock_cnt_qxu_lofx[0]     LUT2      I0       In      -         1.449 r     -         
u_hpram_top.u_hpram_sync.lock_cnt_qxu_lofx[0]     LUT2      F        Out     1.032     2.481 f     -         
lock_cnt_qxu_lofx[0]                              Net       -        -       1.021     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[0]        ALU       I0       In      -         3.502 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[0]        ALU       COUT     Out     0.958     4.460 f     -         
lock_cnt_cry[0]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[1]        ALU       CIN      In      -         4.460 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[1]        ALU       COUT     Out     0.057     4.517 f     -         
lock_cnt_cry[1]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[2]        ALU       CIN      In      -         4.517 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[2]        ALU       COUT     Out     0.057     4.574 f     -         
lock_cnt_cry[2]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[3]        ALU       CIN      In      -         4.574 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[3]        ALU       COUT     Out     0.057     4.631 f     -         
lock_cnt_cry[3]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[4]        ALU       CIN      In      -         4.631 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[4]        ALU       COUT     Out     0.057     4.688 f     -         
lock_cnt_cry[4]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[5]        ALU       CIN      In      -         4.688 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[5]        ALU       COUT     Out     0.057     4.745 f     -         
lock_cnt_cry[5]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[6]        ALU       CIN      In      -         4.745 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[6]        ALU       COUT     Out     0.057     4.802 f     -         
lock_cnt_cry[6]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[7]        ALU       CIN      In      -         4.802 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[7]        ALU       COUT     Out     0.057     4.859 f     -         
lock_cnt_cry[7]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[8]        ALU       CIN      In      -         4.859 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[8]        ALU       COUT     Out     0.057     4.916 f     -         
lock_cnt_cry[8]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[9]        ALU       CIN      In      -         4.916 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[9]        ALU       COUT     Out     0.057     4.973 f     -         
lock_cnt_cry[9]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[10]       ALU       CIN      In      -         4.973 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[10]       ALU       COUT     Out     0.057     5.030 f     -         
lock_cnt_cry[10]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[11]       ALU       CIN      In      -         5.030 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[11]       ALU       COUT     Out     0.057     5.087 f     -         
lock_cnt_cry[11]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[12]       ALU       CIN      In      -         5.087 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[12]       ALU       COUT     Out     0.057     5.144 f     -         
lock_cnt_cry[12]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[13]       ALU       CIN      In      -         5.144 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[13]       ALU       COUT     Out     0.057     5.201 f     -         
lock_cnt_cry[13]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[14]       ALU       CIN      In      -         5.201 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[14]       ALU       COUT     Out     0.057     5.258 f     -         
lock_cnt_cry[14]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_s_0[15]         ALU       CIN      In      -         5.258 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_s_0[15]         ALU       SUM      Out     0.563     5.821 f     -         
lock_cnt_s[15]                                    Net       -        -       1.021     -           1         
u_hpram_top.u_hpram_sync.lock_cnt[15]             DFFCE     D        In      -         6.842 f     -         
=============================================================================================================
Total path delay (propagation time + setup) of 6.975 is 3.851(55.2%) logic and 3.124(44.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.212

    - Propagation time:                      6.791
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.580

    Number of logic level(s):                16
    Starting point:                          u_hpram_top.u_hpram_sync.lock_cnt[1] / Q
    Ending point:                            u_hpram_top.u_hpram_sync.lock_cnt[15] / D
    The start point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK
    The end   point is clocked by            HyperRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=3.172 period=6.345) on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_sync.lock_cnt[1]              DFFCE     Q        Out     0.367     0.367 r     -         
lock_cnt[1]                                       Net       -        -       1.021     -           2         
u_hpram_top.u_hpram_sync.lock_cnt_qxu_lofx[1]     LUT2      I1       In      -         1.388 r     -         
u_hpram_top.u_hpram_sync.lock_cnt_qxu_lofx[1]     LUT2      F        Out     1.099     2.487 f     -         
lock_cnt_qxu_lofx[1]                              Net       -        -       1.021     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[1]        ALU       I0       In      -         3.508 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[1]        ALU       COUT     Out     0.958     4.466 f     -         
lock_cnt_cry[1]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[2]        ALU       CIN      In      -         4.466 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[2]        ALU       COUT     Out     0.057     4.523 f     -         
lock_cnt_cry[2]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[3]        ALU       CIN      In      -         4.523 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[3]        ALU       COUT     Out     0.057     4.580 f     -         
lock_cnt_cry[3]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[4]        ALU       CIN      In      -         4.580 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[4]        ALU       COUT     Out     0.057     4.637 f     -         
lock_cnt_cry[4]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[5]        ALU       CIN      In      -         4.637 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[5]        ALU       COUT     Out     0.057     4.694 f     -         
lock_cnt_cry[5]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[6]        ALU       CIN      In      -         4.694 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[6]        ALU       COUT     Out     0.057     4.751 f     -         
lock_cnt_cry[6]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[7]        ALU       CIN      In      -         4.751 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[7]        ALU       COUT     Out     0.057     4.808 f     -         
lock_cnt_cry[7]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[8]        ALU       CIN      In      -         4.808 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[8]        ALU       COUT     Out     0.057     4.865 f     -         
lock_cnt_cry[8]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[9]        ALU       CIN      In      -         4.865 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[9]        ALU       COUT     Out     0.057     4.922 f     -         
lock_cnt_cry[9]                                   Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[10]       ALU       CIN      In      -         4.922 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[10]       ALU       COUT     Out     0.057     4.979 f     -         
lock_cnt_cry[10]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[11]       ALU       CIN      In      -         4.979 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[11]       ALU       COUT     Out     0.057     5.036 f     -         
lock_cnt_cry[11]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[12]       ALU       CIN      In      -         5.036 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[12]       ALU       COUT     Out     0.057     5.093 f     -         
lock_cnt_cry[12]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[13]       ALU       CIN      In      -         5.093 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[13]       ALU       COUT     Out     0.057     5.150 f     -         
lock_cnt_cry[13]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[14]       ALU       CIN      In      -         5.150 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_cry_0[14]       ALU       COUT     Out     0.057     5.207 f     -         
lock_cnt_cry[14]                                  Net       -        -       0.000     -           1         
u_hpram_top.u_hpram_sync.lock_cnt_s_0[15]         ALU       CIN      In      -         5.207 f     -         
u_hpram_top.u_hpram_sync.lock_cnt_s_0[15]         ALU       SUM      Out     0.563     5.770 f     -         
lock_cnt_s[15]                                    Net       -        -       1.021     -           1         
u_hpram_top.u_hpram_sync.lock_cnt[15]             DFFCE     D        In      -         6.791 f     -         
=============================================================================================================
Total path delay (propagation time + setup) of 6.924 is 3.861(55.8%) logic and 3.063(44.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                        Starting                                                                                                     Arrival           
Instance                                                                                Reference                                                             Type      Pin     Net                  Time        Slack 
                                                                                        Clock                                                                                                                          
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     Q       rd_data_ctrl_reg     0.367       -1.400
u_hpram_top.rd_data_d[11]                                                               _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       rd_data_d[11]        0.367       -1.215
u_hpram_top.u_hpram_wd.step[1]                                                          _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       step[1]              0.367       -1.194
u_hpram_top.rd_data_d[1]                                                                _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       rd_data_d[1]         0.367       -1.148
u_hpram_top.rd_data_d[9]                                                                _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       rd_data_d[9]         0.367       -1.148
u_hpram_top.u_hpram_wd.step[2]                                                          _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       step[2]              0.367       -1.137
u_hpram_top.rd_data_d[8]                                                                _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       rd_data_d[8]         0.367       -1.081
u_hpram_top.u_hpram_wd.step[3]                                                          _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       step[3]              0.367       -1.080
u_hpram_top.rd_data_d[14]                                                               _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       rd_data_d[14]        0.367       -1.027
u_hpram_top.u_hpram_wd.step[4]                                                          _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       step[4]              0.367       -1.023
=======================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                            Starting                                                                                                           Required           
Instance                                                                                    Reference                                                             Type       Pin        Net                    Time         Slack 
                                                                                            Clock                                                                                                                                 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     SDPX9B     RESETB     rd_data_ctrl_reg_i     2.041        -1.400
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[0\]\.dq_oser4     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     OSER4      D1         wr_dq_1[2]             7.798        -1.400
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[0\]\.dq_oser4     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     OSER4      D2         wr_dq_1[1]             7.798        -1.400
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[0\]\.dq_oser4     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     OSER4      D3         wr_dq_1[0]             7.798        -1.400
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[1\]\.dq_oser4     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     OSER4      D2         wr_dq_1[5]             7.798        -1.400
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[2\]\.dq_oser4     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     OSER4      D2         wr_dq_1[9]             7.798        -1.400
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[2\]\.dq_oser4     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     OSER4      D3         wr_dq_1[8]             7.798        -1.400
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[3\]\.dq_oser4     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     OSER4      D2         wr_dq_1[13]            7.798        -1.400
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[3\]\.dq_oser4     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     OSER4      D3         wr_dq_1[12]            7.798        -1.400
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[4\]\.dq_oser4     _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock     OSER4      D2         wr_dq_1[17]            7.798        -1.400
==================================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      9.197
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.400

    Number of logic level(s):                4
    Starting point:                          u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg / Q
    Ending point:                            u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[7\]\.dq_oser4 / D2
    The start point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin PCLK

Instance / Net                                                                                         Pin        Pin               Arrival     No. of    
Name                                                                                        Type       Name       Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg         DFFCE      Q          Out     0.367     0.367 r     -         
rd_data_ctrl_reg                                                                            Net        -          -       1.021     -           3         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        I          In      -         1.388 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        O          Out     1.032     2.420 f     -         
rd_data_ctrl_reg_i                                                                          Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     RESETB     In      -         3.441 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     DO[33]     Out     0.818     4.259 r     -         
mem_mask_mem_mask_0_0_DO[33]                                                                Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[29]                       LUT4       I0         In      -         5.280 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[29]                       LUT4       F          Out     1.032     6.312 f     -         
N_249                                                                                       Net        -          -       0.766     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[29]                         LUT3       I1         In      -         7.077 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[29]                         LUT3       F          Out     1.099     8.177 f     -         
wr_dq_1[29]                                                                                 Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[7\]\.dq_oser4     OSER4      D2         In      -         9.197 f     -         
==========================================================================================================================================================
Total path delay (propagation time + setup) of 9.331 is 4.481(48.0%) logic and 4.850(52.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      9.197
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.400

    Number of logic level(s):                4
    Starting point:                          u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg / Q
    Ending point:                            u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[0\]\.dq_oser4 / D3
    The start point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin PCLK

Instance / Net                                                                                         Pin        Pin               Arrival     No. of    
Name                                                                                        Type       Name       Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg         DFFCE      Q          Out     0.367     0.367 r     -         
rd_data_ctrl_reg                                                                            Net        -          -       1.021     -           3         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        I          In      -         1.388 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        O          Out     1.032     2.420 f     -         
rd_data_ctrl_reg_i                                                                          Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     RESETB     In      -         3.441 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     DO[4]      Out     0.818     4.259 r     -         
mem_mask_mem_mask_0_0_DO[4]                                                                 Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[0]                        LUT4       I0         In      -         5.280 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[0]                        LUT4       F          Out     1.032     6.312 f     -         
N_229                                                                                       Net        -          -       0.766     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[0]                          LUT3       I1         In      -         7.077 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[0]                          LUT3       F          Out     1.099     8.177 f     -         
wr_dq_1[0]                                                                                  Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[0\]\.dq_oser4     OSER4      D3         In      -         9.197 f     -         
==========================================================================================================================================================
Total path delay (propagation time + setup) of 9.331 is 4.481(48.0%) logic and 4.850(52.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      9.197
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.400

    Number of logic level(s):                4
    Starting point:                          u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg / Q
    Ending point:                            u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[0\]\.dq_oser4 / D2
    The start point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin PCLK

Instance / Net                                                                                         Pin        Pin               Arrival     No. of    
Name                                                                                        Type       Name       Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg         DFFCE      Q          Out     0.367     0.367 r     -         
rd_data_ctrl_reg                                                                            Net        -          -       1.021     -           3         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        I          In      -         1.388 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        O          Out     1.032     2.420 f     -         
rd_data_ctrl_reg_i                                                                          Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     RESETB     In      -         3.441 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     DO[5]      Out     0.818     4.259 r     -         
mem_mask_mem_mask_0_0_DO[5]                                                                 Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[1]                        LUT4       I0         In      -         5.280 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[1]                        LUT4       F          Out     1.032     6.312 f     -         
N_230                                                                                       Net        -          -       0.766     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[1]                          LUT3       I1         In      -         7.077 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[1]                          LUT3       F          Out     1.099     8.177 f     -         
wr_dq_1[1]                                                                                  Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[0\]\.dq_oser4     OSER4      D2         In      -         9.197 f     -         
==========================================================================================================================================================
Total path delay (propagation time + setup) of 9.331 is 4.481(48.0%) logic and 4.850(52.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      9.197
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.400

    Number of logic level(s):                4
    Starting point:                          u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg / Q
    Ending point:                            u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[0\]\.dq_oser4 / D1
    The start point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin PCLK

Instance / Net                                                                                         Pin        Pin               Arrival     No. of    
Name                                                                                        Type       Name       Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg         DFFCE      Q          Out     0.367     0.367 r     -         
rd_data_ctrl_reg                                                                            Net        -          -       1.021     -           3         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        I          In      -         1.388 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        O          Out     1.032     2.420 f     -         
rd_data_ctrl_reg_i                                                                          Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     RESETB     In      -         3.441 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     DO[6]      Out     0.818     4.259 r     -         
mem_mask_mem_mask_0_0_DO[6]                                                                 Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[2]                        LUT4       I0         In      -         5.280 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[2]                        LUT4       F          Out     1.032     6.312 f     -         
N_231                                                                                       Net        -          -       0.766     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[2]                          LUT3       I1         In      -         7.077 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[2]                          LUT3       F          Out     1.099     8.177 f     -         
wr_dq_1[2]                                                                                  Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[0\]\.dq_oser4     OSER4      D1         In      -         9.197 f     -         
==========================================================================================================================================================
Total path delay (propagation time + setup) of 9.331 is 4.481(48.0%) logic and 4.850(52.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      9.197
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.400

    Number of logic level(s):                4
    Starting point:                          u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg / Q
    Ending point:                            u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[1\]\.dq_oser4 / D2
    The start point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin PCLK

Instance / Net                                                                                         Pin        Pin               Arrival     No. of    
Name                                                                                        Type       Name       Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg         DFFCE      Q          Out     0.367     0.367 r     -         
rd_data_ctrl_reg                                                                            Net        -          -       1.021     -           3         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        I          In      -         1.388 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.byte128wr\.rd_data_ctrl_reg_i       INV        O          Out     1.032     2.420 f     -         
rd_data_ctrl_reg_i                                                                          Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     RESETB     In      -         3.441 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.mem_mask_mem_mask_0_0               SDPX9B     DO[9]      Out     0.818     4.259 r     -         
mem_mask_mem_mask_0_0_DO[9]                                                                 Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[5]                        LUT4       I0         In      -         5.280 r     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1_0[5]                        LUT4       F          Out     1.032     6.312 f     -         
N_233                                                                                       Net        -          -       0.766     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[5]                          LUT3       I1         In      -         7.077 f     -         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.wr_dq_1[5]                          LUT3       F          Out     1.099     8.177 f     -         
wr_dq_1[5]                                                                                  Net        -          -       1.021     -           1         
u_hpram_top.u_hpram_wd.data_lane_gen\[0\]\.u_hpram_lane.oserdes_data_gen\[1\]\.dq_oser4     OSER4      D2         In      -         9.197 f     -         
==========================================================================================================================================================
Total path delay (propagation time + setup) of 9.331 is 4.481(48.0%) logic and 4.850(52.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                       Starting                                             Arrival           
Instance               Reference     Type       Pin         Net             Time        Slack 
                       Clock                                                                  
----------------------------------------------------------------------------------------------
u_hpram_top.u_dll      System        DLL        STEP[0]     dll_step[0]     0.000       -0.740
u_hpram_top.u_dll      System        DLL        STEP[1]     dll_step[1]     0.000       -0.683
u_hpram_top.u_dll      System        DLL        STEP[2]     dll_step[2]     0.000       -0.626
u_hpram_top.u_dll      System        DLL        STEP[3]     dll_step[3]     0.000       -0.569
u_hpram_top.u_dll      System        DLL        STEP[4]     dll_step[4]     0.000       -0.512
u_hpram_top.u_dll      System        DLL        STEP[5]     dll_step[5]     0.000       -0.455
u_hpram_top.u_dll      System        DLL        STEP[6]     dll_step[6]     0.000       -0.398
u_hpram_top.u_dll      System        DLL        STEP[7]     dll_step[7]     0.000       -0.341
u_hpram_top.clkdiv     System        CLKDIV     CLKOUT      clk_out_i       0.000       2.851 
u_hpram_top.u_dll      System        DLL        LOCK        dll_lock        0.000       4.159 
==============================================================================================


Ending Points with Worst Slack
******************************

                                   Starting                                          Required           
Instance                           Reference     Type     Pin     Net                Time         Slack 
                                   Clock                                                                
--------------------------------------------------------------------------------------------------------
u_hpram_top.u_hpram_wd.step[8]     System        DFFC     D       step_3[8]          7.798        -0.740
u_hpram_top.u_hpram_wd.step[7]     System        DFFC     D       step_3[7]          7.798        -0.683
u_hpram_top.u_hpram_wd.step[6]     System        DFFC     D       step_3[6]          7.798        -0.626
u_hpram_top.u_hpram_wd.step[5]     System        DFFC     D       step_3[5]          7.798        -0.569
u_hpram_top.u_hpram_wd.step[4]     System        DFFC     D       step_3[4]          7.798        -0.512
u_hpram_top.u_hpram_wd.step[3]     System        DFFC     D       step_3[3]          7.798        -0.455
u_hpram_top.u_hpram_wd.step[2]     System        DFFC     D       step_3[2]          7.798        -0.398
u_hpram_top.u_hpram_wd.step[1]     System        DFFC     D       step_3[1]          7.798        -0.341
u_hpram_top.rd_data_d[0]           System        DFFC     D       rd_data_d_3[0]     7.798        2.851 
u_hpram_top.rd_data_d[1]           System        DFFC     D       rd_data_d_3[1]     7.798        2.851 
========================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      8.538
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.740

    Number of logic level(s):                18
    Starting point:                          u_hpram_top.u_dll / STEP[0]
    Ending point:                            u_hpram_top.u_hpram_wd.step[8] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK

Instance / Net                                       Pin         Pin               Arrival     No. of    
Name                                        Type     Name        Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
u_hpram_top.u_dll                           DLL      STEP[0]     Out     0.000     0.000 r     -         
dll_step[0]                                 Net      -           -       1.021     -           2         
u_hpram_top.u_hpram_wd.un1_step_cry_1_0     ALU      I0          In      -         1.021 r     -         
u_hpram_top.u_hpram_wd.un1_step_cry_1_0     ALU      COUT        Out     0.958     1.979 f     -         
un1_step_cry_1                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_2_0     ALU      CIN         In      -         1.979 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_2_0     ALU      COUT        Out     0.057     2.036 f     -         
un1_step_cry_2                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      CIN         In      -         2.036 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      COUT        Out     0.057     2.093 f     -         
un1_step_cry_3                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      CIN         In      -         2.093 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      COUT        Out     0.057     2.150 f     -         
un1_step_cry_4                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      CIN         In      -         2.150 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      COUT        Out     0.057     2.207 f     -         
un1_step_cry_5                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      CIN         In      -         2.207 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      COUT        Out     0.057     2.264 f     -         
un1_step_cry_6                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      CIN         In      -         2.264 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      COUT        Out     0.057     2.321 f     -         
un1_step_cry_7                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      CIN         In      -         2.321 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      COUT        Out     0.057     2.378 f     -         
un1_step_cry_8                              Net      -           -       1.549     -           1         
u_hpram_top.u_hpram_wd.step8                LUT2     I1          In      -         3.927 f     -         
u_hpram_top.u_hpram_wd.step8                LUT2     F           Out     1.099     5.026 f     -         
step8                                       Net      -           -       1.472     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      CIN         In      -         6.498 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      COUT        Out     0.057     6.555 f     -         
step_3_cry_0                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      CIN         In      -         6.555 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      COUT        Out     0.057     6.612 f     -         
step_3_cry_1                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      CIN         In      -         6.612 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      COUT        Out     0.057     6.669 f     -         
step_3_cry_2                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      CIN         In      -         6.669 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      COUT        Out     0.057     6.726 f     -         
step_3_cry_3                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      CIN         In      -         6.726 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      COUT        Out     0.057     6.783 f     -         
step_3_cry_4                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      CIN         In      -         6.783 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      COUT        Out     0.057     6.840 f     -         
step_3_cry_5                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      CIN         In      -         6.840 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      COUT        Out     0.057     6.897 f     -         
step_3_cry_6                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_7_0       ALU      CIN         In      -         6.897 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_7_0       ALU      COUT        Out     0.057     6.954 f     -         
step_3_cry_7                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_s_8_0         ALU      CIN         In      -         6.954 f     -         
u_hpram_top.u_hpram_wd.step_3_s_8_0         ALU      SUM         Out     0.563     7.517 f     -         
step_3[8]                                   Net      -           -       1.021     -           1         
u_hpram_top.u_hpram_wd.step[8]              DFFC     D           In      -         8.538 f     -         
=========================================================================================================
Total path delay (propagation time + setup) of 8.671 is 3.608(41.6%) logic and 5.063(58.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      8.481
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.683

    Number of logic level(s):                17
    Starting point:                          u_hpram_top.u_dll / STEP[1]
    Ending point:                            u_hpram_top.u_hpram_wd.step[8] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK

Instance / Net                                       Pin         Pin               Arrival     No. of    
Name                                        Type     Name        Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
u_hpram_top.u_dll                           DLL      STEP[1]     Out     0.000     0.000 r     -         
dll_step[1]                                 Net      -           -       1.021     -           2         
u_hpram_top.u_hpram_wd.un1_step_cry_2_0     ALU      I0          In      -         1.021 r     -         
u_hpram_top.u_hpram_wd.un1_step_cry_2_0     ALU      COUT        Out     0.958     1.979 f     -         
un1_step_cry_2                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      CIN         In      -         1.979 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      COUT        Out     0.057     2.036 f     -         
un1_step_cry_3                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      CIN         In      -         2.036 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      COUT        Out     0.057     2.093 f     -         
un1_step_cry_4                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      CIN         In      -         2.093 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      COUT        Out     0.057     2.150 f     -         
un1_step_cry_5                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      CIN         In      -         2.150 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      COUT        Out     0.057     2.207 f     -         
un1_step_cry_6                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      CIN         In      -         2.207 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      COUT        Out     0.057     2.264 f     -         
un1_step_cry_7                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      CIN         In      -         2.264 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      COUT        Out     0.057     2.321 f     -         
un1_step_cry_8                              Net      -           -       1.549     -           1         
u_hpram_top.u_hpram_wd.step8                LUT2     I1          In      -         3.870 f     -         
u_hpram_top.u_hpram_wd.step8                LUT2     F           Out     1.099     4.969 f     -         
step8                                       Net      -           -       1.472     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      CIN         In      -         6.441 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      COUT        Out     0.057     6.498 f     -         
step_3_cry_0                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      CIN         In      -         6.498 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      COUT        Out     0.057     6.555 f     -         
step_3_cry_1                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      CIN         In      -         6.555 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      COUT        Out     0.057     6.612 f     -         
step_3_cry_2                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      CIN         In      -         6.612 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      COUT        Out     0.057     6.669 f     -         
step_3_cry_3                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      CIN         In      -         6.669 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      COUT        Out     0.057     6.726 f     -         
step_3_cry_4                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      CIN         In      -         6.726 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      COUT        Out     0.057     6.783 f     -         
step_3_cry_5                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      CIN         In      -         6.783 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      COUT        Out     0.057     6.840 f     -         
step_3_cry_6                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_7_0       ALU      CIN         In      -         6.840 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_7_0       ALU      COUT        Out     0.057     6.897 f     -         
step_3_cry_7                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_s_8_0         ALU      CIN         In      -         6.897 f     -         
u_hpram_top.u_hpram_wd.step_3_s_8_0         ALU      SUM         Out     0.563     7.460 f     -         
step_3[8]                                   Net      -           -       1.021     -           1         
u_hpram_top.u_hpram_wd.step[8]              DFFC     D           In      -         8.481 f     -         
=========================================================================================================
Total path delay (propagation time + setup) of 8.614 is 3.551(41.2%) logic and 5.063(58.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      8.481
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.683

    Number of logic level(s):                17
    Starting point:                          u_hpram_top.u_dll / STEP[0]
    Ending point:                            u_hpram_top.u_hpram_wd.step[7] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK

Instance / Net                                       Pin         Pin               Arrival     No. of    
Name                                        Type     Name        Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
u_hpram_top.u_dll                           DLL      STEP[0]     Out     0.000     0.000 r     -         
dll_step[0]                                 Net      -           -       1.021     -           2         
u_hpram_top.u_hpram_wd.un1_step_cry_1_0     ALU      I0          In      -         1.021 r     -         
u_hpram_top.u_hpram_wd.un1_step_cry_1_0     ALU      COUT        Out     0.958     1.979 f     -         
un1_step_cry_1                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_2_0     ALU      CIN         In      -         1.979 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_2_0     ALU      COUT        Out     0.057     2.036 f     -         
un1_step_cry_2                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      CIN         In      -         2.036 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      COUT        Out     0.057     2.093 f     -         
un1_step_cry_3                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      CIN         In      -         2.093 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      COUT        Out     0.057     2.150 f     -         
un1_step_cry_4                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      CIN         In      -         2.150 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      COUT        Out     0.057     2.207 f     -         
un1_step_cry_5                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      CIN         In      -         2.207 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      COUT        Out     0.057     2.264 f     -         
un1_step_cry_6                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      CIN         In      -         2.264 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      COUT        Out     0.057     2.321 f     -         
un1_step_cry_7                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      CIN         In      -         2.321 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      COUT        Out     0.057     2.378 f     -         
un1_step_cry_8                              Net      -           -       1.549     -           1         
u_hpram_top.u_hpram_wd.step8                LUT2     I1          In      -         3.927 f     -         
u_hpram_top.u_hpram_wd.step8                LUT2     F           Out     1.099     5.026 f     -         
step8                                       Net      -           -       1.472     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      CIN         In      -         6.498 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      COUT        Out     0.057     6.555 f     -         
step_3_cry_0                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      CIN         In      -         6.555 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      COUT        Out     0.057     6.612 f     -         
step_3_cry_1                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      CIN         In      -         6.612 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      COUT        Out     0.057     6.669 f     -         
step_3_cry_2                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      CIN         In      -         6.669 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      COUT        Out     0.057     6.726 f     -         
step_3_cry_3                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      CIN         In      -         6.726 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      COUT        Out     0.057     6.783 f     -         
step_3_cry_4                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      CIN         In      -         6.783 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      COUT        Out     0.057     6.840 f     -         
step_3_cry_5                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      CIN         In      -         6.840 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      COUT        Out     0.057     6.897 f     -         
step_3_cry_6                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_7_0       ALU      CIN         In      -         6.897 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_7_0       ALU      SUM         Out     0.563     7.460 f     -         
step_3[7]                                   Net      -           -       1.021     -           1         
u_hpram_top.u_hpram_wd.step[7]              DFFC     D           In      -         8.481 f     -         
=========================================================================================================
Total path delay (propagation time + setup) of 8.614 is 3.551(41.2%) logic and 5.063(58.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      8.424
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.626

    Number of logic level(s):                16
    Starting point:                          u_hpram_top.u_dll / STEP[2]
    Ending point:                            u_hpram_top.u_hpram_wd.step[8] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK

Instance / Net                                       Pin         Pin               Arrival     No. of    
Name                                        Type     Name        Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
u_hpram_top.u_dll                           DLL      STEP[2]     Out     0.000     0.000 r     -         
dll_step[2]                                 Net      -           -       1.021     -           2         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      I0          In      -         1.021 r     -         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      COUT        Out     0.958     1.979 f     -         
un1_step_cry_3                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      CIN         In      -         1.979 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      COUT        Out     0.057     2.036 f     -         
un1_step_cry_4                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      CIN         In      -         2.036 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      COUT        Out     0.057     2.093 f     -         
un1_step_cry_5                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      CIN         In      -         2.093 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      COUT        Out     0.057     2.150 f     -         
un1_step_cry_6                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      CIN         In      -         2.150 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      COUT        Out     0.057     2.207 f     -         
un1_step_cry_7                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      CIN         In      -         2.207 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      COUT        Out     0.057     2.264 f     -         
un1_step_cry_8                              Net      -           -       1.549     -           1         
u_hpram_top.u_hpram_wd.step8                LUT2     I1          In      -         3.813 f     -         
u_hpram_top.u_hpram_wd.step8                LUT2     F           Out     1.099     4.912 f     -         
step8                                       Net      -           -       1.472     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      CIN         In      -         6.384 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      COUT        Out     0.057     6.441 f     -         
step_3_cry_0                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      CIN         In      -         6.441 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      COUT        Out     0.057     6.498 f     -         
step_3_cry_1                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      CIN         In      -         6.498 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      COUT        Out     0.057     6.555 f     -         
step_3_cry_2                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      CIN         In      -         6.555 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      COUT        Out     0.057     6.612 f     -         
step_3_cry_3                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      CIN         In      -         6.612 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      COUT        Out     0.057     6.669 f     -         
step_3_cry_4                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      CIN         In      -         6.669 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      COUT        Out     0.057     6.726 f     -         
step_3_cry_5                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      CIN         In      -         6.726 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      COUT        Out     0.057     6.783 f     -         
step_3_cry_6                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_7_0       ALU      CIN         In      -         6.783 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_7_0       ALU      COUT        Out     0.057     6.840 f     -         
step_3_cry_7                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_s_8_0         ALU      CIN         In      -         6.840 f     -         
u_hpram_top.u_hpram_wd.step_3_s_8_0         ALU      SUM         Out     0.563     7.403 f     -         
step_3[8]                                   Net      -           -       1.021     -           1         
u_hpram_top.u_hpram_wd.step[8]              DFFC     D           In      -         8.424 f     -         
=========================================================================================================
Total path delay (propagation time + setup) of 8.557 is 3.494(40.8%) logic and 5.063(59.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      7.931
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.798

    - Propagation time:                      8.424
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.626

    Number of logic level(s):                16
    Starting point:                          u_hpram_top.u_dll / STEP[0]
    Ending point:                            u_hpram_top.u_hpram_wd.step[6] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=3.965 period=7.931) on pin CLK

Instance / Net                                       Pin         Pin               Arrival     No. of    
Name                                        Type     Name        Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
u_hpram_top.u_dll                           DLL      STEP[0]     Out     0.000     0.000 r     -         
dll_step[0]                                 Net      -           -       1.021     -           2         
u_hpram_top.u_hpram_wd.un1_step_cry_1_0     ALU      I0          In      -         1.021 r     -         
u_hpram_top.u_hpram_wd.un1_step_cry_1_0     ALU      COUT        Out     0.958     1.979 f     -         
un1_step_cry_1                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_2_0     ALU      CIN         In      -         1.979 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_2_0     ALU      COUT        Out     0.057     2.036 f     -         
un1_step_cry_2                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      CIN         In      -         2.036 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_3_0     ALU      COUT        Out     0.057     2.093 f     -         
un1_step_cry_3                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      CIN         In      -         2.093 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_4_0     ALU      COUT        Out     0.057     2.150 f     -         
un1_step_cry_4                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      CIN         In      -         2.150 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_5_0     ALU      COUT        Out     0.057     2.207 f     -         
un1_step_cry_5                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      CIN         In      -         2.207 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_6_0     ALU      COUT        Out     0.057     2.264 f     -         
un1_step_cry_6                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      CIN         In      -         2.264 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_7_0     ALU      COUT        Out     0.057     2.321 f     -         
un1_step_cry_7                              Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      CIN         In      -         2.321 f     -         
u_hpram_top.u_hpram_wd.un1_step_cry_8_0     ALU      COUT        Out     0.057     2.378 f     -         
un1_step_cry_8                              Net      -           -       1.549     -           1         
u_hpram_top.u_hpram_wd.step8                LUT2     I1          In      -         3.927 f     -         
u_hpram_top.u_hpram_wd.step8                LUT2     F           Out     1.099     5.026 f     -         
step8                                       Net      -           -       1.472     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      CIN         In      -         6.498 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_0_0       ALU      COUT        Out     0.057     6.555 f     -         
step_3_cry_0                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      CIN         In      -         6.555 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_1_0       ALU      COUT        Out     0.057     6.612 f     -         
step_3_cry_1                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      CIN         In      -         6.612 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_2_0       ALU      COUT        Out     0.057     6.669 f     -         
step_3_cry_2                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      CIN         In      -         6.669 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_3_0       ALU      COUT        Out     0.057     6.726 f     -         
step_3_cry_3                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      CIN         In      -         6.726 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_4_0       ALU      COUT        Out     0.057     6.783 f     -         
step_3_cry_4                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      CIN         In      -         6.783 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_5_0       ALU      COUT        Out     0.057     6.840 f     -         
step_3_cry_5                                Net      -           -       0.000     -           1         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      CIN         In      -         6.840 f     -         
u_hpram_top.u_hpram_wd.step_3_cry_6_0       ALU      SUM         Out     0.563     7.403 f     -         
step_3[6]                                   Net      -           -       1.021     -           1         
u_hpram_top.u_hpram_wd.step[6]              DFFC     D           In      -         8.424 f     -         
=========================================================================================================
Total path delay (propagation time + setup) of 8.557 is 3.494(40.8%) logic and 5.063(59.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 238MB peak: 241MB)


Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 238MB peak: 241MB)

---------------------------------------
Resource Usage Report for HyperRAM_Memory_Interface_Top 

Mapping to part: gw1nsr_4cqfn48p-7
Cell usage:
ALU             110 uses
CLKDIV          1 use
DFFC            237 uses
DFFCE           169 uses
DFFP            5 uses
DFFPE           2 uses
DHCEN           1 use
DLL             1 use
GSR             1 use
IDES4           8 uses
INV             7 uses
IODELAY         10 uses
OSER4           12 uses
SDPX9B          1 use
LUT2            206 uses
LUT3            100 uses
LUT4            242 uses

I/O ports: 112
I/O primitives: 12
IOBUF          9 uses
OBUF           3 uses

I/O Register bits:                  0
Register bits not including I/Os:   413 of 3456 (11%)

RAM/ROM usage summary
Block Rams : 1 of 10 (10%)

Total load per clock:
   _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock: 403
   HyperRAM_Memory_Interface_Top|clk: 33
   _~hpram_top_HyperRAM_Memory_Interface_Top_|clk_x2p_inferred_clock: 22
   _~hpram_wd_HyperRAM_Memory_Interface_Top_|step_derived_clock[0]: 3
   _~hpram_init_HyperRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0]: 8

@S |Mapping Summary:
Total  LUTs: 548 

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 80MB peak: 241MB)

Process took 0h:00m:07s realtime, 0h:00m:07s cputime
# Tue Aug  4 16:22:18 2020

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