#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020 #install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-032 # Tue Aug 4 16:22:01 2020 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\generic\gw1ns.v" (library work) @I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v" (library work) @I:"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v":"E:\IP_verify\1.9.6.0.1\IP_web\psram_hpram_ref_design\Hpram\project\src\hyperram_memory_interface\temp\HYPERRAM\hpram_define.v" (library work) @I:"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v":"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\hpram_local_define.v" (library work) @I:"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v":"E:\IP_verify\1.9.6.0.1\IP_web\psram_hpram_ref_design\Hpram\project\src\hyperram_memory_interface\temp\HYPERRAM\hpram_param.v" (library work) @I:"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v":"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\hpram_local_param.v" (library work) @I::"D:\Gowin\Gowin_V1.9.6.01Beta\IDE\ipcore\HYPERRAM_EMB\data\hpram_code_166.v" (library work) @N:CG346 : hpram_code_166.v(1786) | Read full_case directive. @N:CG347 : hpram_code_166.v(1786) | Read a parallel_case directive. @W:CG286 : hpram_code_166.v(1786) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive. Verilog syntax check successful! Selecting top level module HyperRAM_Memory_Interface_Top Running optimization stage 1 on IODELAY ....... Running optimization stage 1 on OBUF ....... Running optimization stage 1 on OSER4 ....... Running optimization stage 1 on IDES4 ....... Running optimization stage 1 on \~hpram_lane.HyperRAM_Memory_Interface_Top _Z1 ....... Running optimization stage 1 on IOBUF ....... Running optimization stage 1 on \~hpram_wd.HyperRAM_Memory_Interface_Top ....... Running optimization stage 1 on \~hpram_init.HyperRAM_Memory_Interface_Top ....... Running optimization stage 1 on \~hpram_sync.HyperRAM_Memory_Interface_Top ....... Running optimization stage 1 on DLL ....... Running optimization stage 1 on DHCEN ....... Running optimization stage 1 on CLKDIV ....... Running optimization stage 1 on \~hpram_top.HyperRAM_Memory_Interface_Top ....... @N:CG364 : HPRAM_TOP.v(5) | Synthesizing module HyperRAM_Memory_Interface_Top in library work. Running optimization stage 1 on HyperRAM_Memory_Interface_Top ....... Running optimization stage 2 on HyperRAM_Memory_Interface_Top ....... Running optimization stage 2 on \~hpram_top.HyperRAM_Memory_Interface_Top ....... Running optimization stage 2 on CLKDIV ....... Running optimization stage 2 on DHCEN ....... Running optimization stage 2 on DLL ....... Running optimization stage 2 on \~hpram_sync.HyperRAM_Memory_Interface_Top ....... Extracted state machine for register flag State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on \~hpram_init.HyperRAM_Memory_Interface_Top ....... Extracted state machine for register c_state State machine has 11 reachable states with original encodings of: 00000000001 00000000010 00000000100 00000001000 00000010000 00000100000 00001000000 00010000000 00100000000 01000000000 10000000000 Running optimization stage 2 on IOBUF ....... Running optimization stage 2 on IDES4 ....... Running optimization stage 2 on \~hpram_lane.HyperRAM_Memory_Interface_Top _Z1 ....... Running optimization stage 2 on OSER4 ....... Running optimization stage 2 on \~hpram_wd.HyperRAM_Memory_Interface_Top ....... Running optimization stage 2 on OBUF ....... Running optimization stage 2 on IODELAY ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 100MB peak: 102MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Aug 4 16:22:04 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: d:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:NF107 : hpram_top.v(5) | Selected library: work cell: HyperRAM_Memory_Interface_Top view verilog as top level @N:NF107 : hpram_top.v(5) | Selected library: work cell: HyperRAM_Memory_Interface_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Aug 4 16:22:05 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: hyperram_memory_interface_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 22MB peak: 22MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Aug 4 16:22:05 2020 ###########################################################]