Project Settings
Project Name HYPERRAM Device Name rev_1: GOWIN-GW1NSR : GW1NSR_4C
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 1 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 10 1 0 - 00m:04s - 2020/8/4
16:22:05
(premap)Complete 5 0 0 0m:02s 0m:02s 229MB 2020/8/4
16:22:09
(fpga_mapper)Complete 13 8 0 0m:07s 0m:07s 241MB 2020/8/4
16:22:18
Multi-srs Generator Complete2020/8/4
16:22:06

Area Summary
I/O ports (io_port) 112 Non I/O Register bits (non_io_reg) 413 (11%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 1 (10) Block Multipliers (dsp_used) 0 (8)
LUTs (total_luts) 548 (11%)

Timing Summary
Clock NameReq FreqEst FreqSlack
HyperRAM_Memory_Interface_Top|clk157.6 MHz134.0 MHz-1.120
_~hpram_init_HyperRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0]0.1 MHzNANA
_~hpram_top_HyperRAM_Memory_Interface_Top_|clk_out_inferred_clock126.1 MHz107.2 MHz-1.400
_~hpram_top_HyperRAM_Memory_Interface_Top_|clk_x2p_inferred_clock100.0 MHzNANA
_~hpram_wd_HyperRAM_Memory_Interface_Top_|step_derived_clock[0]0.1 MHzNANA
System100.0 MHz93.1 MHz-0.740

Optimizations Summary
Combined Clock Conversion 1 / 4