Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\_FPGA_Proj\GOWIN\HyperRAM\project\src\hpram_syn_top.v
D:\_FPGA_Proj\GOWIN\HyperRAM\project\src\hpram_test.v
D:\_FPGA_Proj\GOWIN\HyperRAM\project\src\hyperram_memory_interface\hyperram_memory_interface.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.03
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Mon May 09 16:03:32 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module hpram_syn_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.836s, Peak memory usage = 77.840MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 77.840MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 77.840MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 77.840MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 77.840MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 77.840MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 77.840MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 77.840MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 77.840MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 77.840MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 77.840MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 88.238MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.223s, Peak memory usage = 88.238MB
Generate output files:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 88.238MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 88.238MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4
Embedded Port 13
I/O Buf 17
    IBUF 2
    OBUF 6
    IOBUF 9
Register 646
    DFFP 6
    DFFPE 2
    DFFC 309
    DFFCE 329
LUT 856
    LUT2 233
    LUT3 188
    LUT4 435
ALU 124
    ALU 124
INV 7
    INV 7
IOLOGIC 30
    IDES4 8
    OSER4 12
    IODELAY 10
BSRAM 1
    SDPX9B 1
CLOCK 3
    CLKDIV 1
    DHCEN 1
    PLLVR 1

Resource Utilization Summary

Resource Usage Utilization
Logic 987(863 LUTs, 124 ALUs) / 4608 21%
Register 646 / 3609 18%
  --Register as Latch 0 / 3609 0%
  --Register as FF 646 / 3609 18%
BSRAM 1 / 10 10%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 14.286 70.0 0.000 7.143 clk_ibuf/I
pllvr_inst/CLKOUT.default_gen_clk Generated 5.952 168.0 0.000 2.976 clk_ibuf/I clk pllvr_inst/CLKOUT
pllvr_inst/CLKOUTP.default_gen_clk Generated 5.952 168.0 0.000 2.976 clk_ibuf/I clk pllvr_inst/CLKOUTP
pllvr_inst/CLKOUTD.default_gen_clk Generated 11.905 84.0 0.000 5.952 clk_ibuf/I clk pllvr_inst/CLKOUTD
pllvr_inst/CLKOUTD3.default_gen_clk Generated 17.857 56.0 0.000 8.929 clk_ibuf/I clk pllvr_inst/CLKOUTD3
u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Generated 11.905 84.0 0.000 5.952 pllvr_inst/CLKOUT pllvr_inst/CLKOUT.default_gen_clk u_hpram_top/u_hpram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 70.0(MHz) 195.5(MHz) 5 TOP
2 u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk 84.0(MHz) 176.3(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.277
Data Arrival Time 12.394
Data Required Time 12.117
From u_hpram_top/u_hpram_top/u_dll
To u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[8]
Launch Clk pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.952 0.000 pllvr_inst/CLKOUT.default_gen_clk
7.255 1.302 tCL RR 1 pllvr_inst/CLKOUT
7.524 0.269 tNET RR 3 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.708 0.184 tINS RR 22 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
7.977 0.269 tNET RR 8 u_hpram_top/u_hpram_top/u_dll/CLKIN
8.396 0.420 tINS RF 2 u_hpram_top/u_hpram_top/u_dll/STEP[0]
8.752 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
9.462 0.710 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
9.462 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
9.504 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
9.504 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
9.546 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
9.546 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
9.589 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
9.589 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
9.631 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
9.631 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
9.673 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
9.673 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
9.715 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
9.715 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
9.758 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
10.113 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/I1
10.928 0.814 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/F
11.283 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/CIN
11.326 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
11.326 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
11.368 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
11.368 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
11.410 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
11.410 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
11.452 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
11.452 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
11.494 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/COUT
11.494 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_5_0/CIN
11.537 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_5_0/COUT
11.537 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_6_0/CIN
11.579 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_6_0/COUT
11.579 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_7_0/CIN
11.621 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_7_0/COUT
11.621 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_s_8_0/CIN
12.038 0.417 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_s_8_0/SUM
12.394 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[8]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
11.905 0.000 u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.174 0.269 tCL RR 635 u_hpram_top/u_hpram_top/clkdiv/CLKOUT
12.443 0.269 tNET RR 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[8]/CLK
12.413 -0.030 tUnc u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[8]
12.117 -0.296 tSu 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[8]
Path Statistics:
Clock Skew: -1.217
Setup Relationship: 5.952
Logic Level: 8
Arrival Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%
Arrival Data Path Delay: cell: 2.995, 63.901%; route: 1.423, 30.359%; tC2Q: 0.269, 5.740%
Required Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%

Path 2

Path Summary:
Slack -0.235
Data Arrival Time 12.352
Data Required Time 12.117
From u_hpram_top/u_hpram_top/u_dll
To u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[7]
Launch Clk pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.952 0.000 pllvr_inst/CLKOUT.default_gen_clk
7.255 1.302 tCL RR 1 pllvr_inst/CLKOUT
7.524 0.269 tNET RR 3 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.708 0.184 tINS RR 22 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
7.977 0.269 tNET RR 8 u_hpram_top/u_hpram_top/u_dll/CLKIN
8.396 0.420 tINS RF 2 u_hpram_top/u_hpram_top/u_dll/STEP[0]
8.752 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
9.462 0.710 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
9.462 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
9.504 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
9.504 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
9.546 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
9.546 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
9.589 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
9.589 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
9.631 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
9.631 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
9.673 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
9.673 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
9.715 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
9.715 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
9.758 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
10.113 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/I1
10.928 0.814 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/F
11.283 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/CIN
11.326 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
11.326 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
11.368 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
11.368 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
11.410 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
11.410 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
11.452 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
11.452 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
11.494 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/COUT
11.494 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_5_0/CIN
11.537 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_5_0/COUT
11.537 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_6_0/CIN
11.579 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_6_0/COUT
11.579 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_7_0/CIN
11.996 0.417 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_7_0/SUM
12.352 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[7]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
11.905 0.000 u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.174 0.269 tCL RR 635 u_hpram_top/u_hpram_top/clkdiv/CLKOUT
12.443 0.269 tNET RR 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[7]/CLK
12.413 -0.030 tUnc u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[7]
12.117 -0.296 tSu 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[7]
Path Statistics:
Clock Skew: -1.217
Setup Relationship: 5.952
Logic Level: 8
Arrival Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%
Arrival Data Path Delay: cell: 2.952, 63.573%; route: 1.423, 30.635%; tC2Q: 0.269, 5.792%
Required Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%

Path 3

Path Summary:
Slack -0.193
Data Arrival Time 12.310
Data Required Time 12.117
From u_hpram_top/u_hpram_top/u_dll
To u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[6]
Launch Clk pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.952 0.000 pllvr_inst/CLKOUT.default_gen_clk
7.255 1.302 tCL RR 1 pllvr_inst/CLKOUT
7.524 0.269 tNET RR 3 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.708 0.184 tINS RR 22 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
7.977 0.269 tNET RR 8 u_hpram_top/u_hpram_top/u_dll/CLKIN
8.396 0.420 tINS RF 2 u_hpram_top/u_hpram_top/u_dll/STEP[0]
8.752 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
9.462 0.710 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
9.462 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
9.504 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
9.504 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
9.546 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
9.546 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
9.589 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
9.589 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
9.631 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
9.631 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
9.673 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
9.673 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
9.715 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
9.715 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
9.758 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
10.113 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/I1
10.928 0.814 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/F
11.283 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/CIN
11.326 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
11.326 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
11.368 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
11.368 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
11.410 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
11.410 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
11.452 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
11.452 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
11.494 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/COUT
11.494 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_5_0/CIN
11.537 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_5_0/COUT
11.537 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_6_0/CIN
11.954 0.417 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_6_0/SUM
12.310 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[6]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
11.905 0.000 u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.174 0.269 tCL RR 635 u_hpram_top/u_hpram_top/clkdiv/CLKOUT
12.443 0.269 tNET RR 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[6]/CLK
12.413 -0.030 tUnc u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[6]
12.117 -0.296 tSu 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[6]
Path Statistics:
Clock Skew: -1.217
Setup Relationship: 5.952
Logic Level: 8
Arrival Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%
Arrival Data Path Delay: cell: 2.910, 63.238%; route: 1.423, 30.917%; tC2Q: 0.269, 5.845%
Required Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%

Path 4

Path Summary:
Slack -0.151
Data Arrival Time 12.267
Data Required Time 12.117
From u_hpram_top/u_hpram_top/u_dll
To u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[5]
Launch Clk pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.952 0.000 pllvr_inst/CLKOUT.default_gen_clk
7.255 1.302 tCL RR 1 pllvr_inst/CLKOUT
7.524 0.269 tNET RR 3 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.708 0.184 tINS RR 22 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
7.977 0.269 tNET RR 8 u_hpram_top/u_hpram_top/u_dll/CLKIN
8.396 0.420 tINS RF 2 u_hpram_top/u_hpram_top/u_dll/STEP[0]
8.752 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
9.462 0.710 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
9.462 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
9.504 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
9.504 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
9.546 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
9.546 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
9.589 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
9.589 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
9.631 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
9.631 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
9.673 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
9.673 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
9.715 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
9.715 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
9.758 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
10.113 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/I1
10.928 0.814 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/F
11.283 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/CIN
11.326 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
11.326 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
11.368 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
11.368 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
11.410 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
11.410 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
11.452 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
11.452 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
11.494 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/COUT
11.494 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_5_0/CIN
11.912 0.417 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_5_0/SUM
12.267 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[5]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
11.905 0.000 u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.174 0.269 tCL RR 635 u_hpram_top/u_hpram_top/clkdiv/CLKOUT
12.443 0.269 tNET RR 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[5]/CLK
12.413 -0.030 tUnc u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[5]
12.117 -0.296 tSu 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[5]
Path Statistics:
Clock Skew: -1.217
Setup Relationship: 5.952
Logic Level: 8
Arrival Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%
Arrival Data Path Delay: cell: 2.868, 62.898%; route: 1.423, 31.203%; tC2Q: 0.269, 5.899%
Required Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%

Path 5

Path Summary:
Slack -0.108
Data Arrival Time 12.225
Data Required Time 12.117
From u_hpram_top/u_hpram_top/u_dll
To u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[4]
Launch Clk pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.952 0.000 pllvr_inst/CLKOUT.default_gen_clk
7.255 1.302 tCL RR 1 pllvr_inst/CLKOUT
7.524 0.269 tNET RR 3 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.708 0.184 tINS RR 22 u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
7.977 0.269 tNET RR 8 u_hpram_top/u_hpram_top/u_dll/CLKIN
8.396 0.420 tINS RF 2 u_hpram_top/u_hpram_top/u_dll/STEP[0]
8.752 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
9.462 0.710 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
9.462 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
9.504 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
9.504 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
9.546 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
9.546 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
9.589 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
9.589 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
9.631 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
9.631 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
9.673 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
9.673 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
9.715 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
9.715 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
9.758 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
10.113 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/I1
10.928 0.814 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step8_cZ/F
11.283 0.356 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/CIN
11.326 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
11.326 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
11.368 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
11.368 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
11.410 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
11.410 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
11.452 0.042 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
11.452 0.000 tNET FF 2 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
11.869 0.417 tINS FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_3_cry_4_0/SUM
12.225 0.356 tNET FF 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[4]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
11.905 0.000 u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.174 0.269 tCL RR 635 u_hpram_top/u_hpram_top/clkdiv/CLKOUT
12.443 0.269 tNET RR 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[4]/CLK
12.413 -0.030 tUnc u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[4]
12.117 -0.296 tSu 1 u_hpram_top/u_hpram_top/u_hpram_wd/step_Z[4]
Path Statistics:
Clock Skew: -1.217
Setup Relationship: 5.952
Logic Level: 8
Arrival Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%
Arrival Data Path Delay: cell: 2.826, 62.551%; route: 1.423, 31.495%; tC2Q: 0.269, 5.954%
Required Clock Path Delay: cell: 0.184, 40.607%; route: 0.269, 59.393%