Timing Messages

Report Title Timing Analysis Report
Design File D:\_FPGA_Proj\GOWIN\HyperRAM\project\impl\gwsynthesis\hpram.vg
Physical Constraints File D:\_FPGA_Proj\GOWIN\HyperRAM\project\src\hpram.cst
Timing Constraint File D:\_FPGA_Proj\GOWIN\HyperRAM\project\src\hpram.sdc
Version V1.9.8.03
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Mon May 09 16:08:05 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C7/I6
Hold Delay Model Fast 1.26V 0C C7/I6
Numbers of Paths Analyzed 2319
Numbers of Endpoints Analyzed 1809
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 9
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk_x1 Base 10.000 100.000 0.000 5.000 clk_x1
clk_x2 Base 5.000 200.000 0.000 2.500 memory_clk
clk Base 14.286 70.000 0.000 7.143 clk_ibuf/I
pllvr_inst/CLKOUTP.default_gen_clk Generated 5.952 168.000 0.000 2.976 clk_ibuf/I clk pllvr_inst/CLKOUTP
pllvr_inst/CLKOUTD.default_gen_clk Generated 11.905 84.000 0.000 5.952 clk_ibuf/I clk pllvr_inst/CLKOUTD
pllvr_inst/CLKOUTD3.default_gen_clk Generated 17.857 56.000 0.000 8.929 clk_ibuf/I clk pllvr_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_x1 100.000(MHz) 114.569(MHz) 3 TOP
2 clk 70.000(MHz) 220.698(MHz) 4 TOP

No timing paths to get frequency of clk_x2!

No timing paths to get frequency of pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of pllvr_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of pllvr_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk_x1 Setup 0.000 0
clk_x1 Hold 0.000 0
clk_x2 Setup 0.000 0
clk_x2 Hold 0.000 0
clk Setup 0.000 0
clk Hold 0.000 0
pllvr_inst/CLKOUTP.default_gen_clk Setup 0.000 0
pllvr_inst/CLKOUTP.default_gen_clk Hold 0.000 0
pllvr_inst/CLKOUTD.default_gen_clk Setup 0.000 0
pllvr_inst/CLKOUTD.default_gen_clk Hold 0.000 0
pllvr_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
pllvr_inst/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -3.479 u_hpram_top/u_hpram_top_0/u_dll/CLKIN u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[8]/D clk_x2:[R] clk_x1:[R] 5.000 0.005 8.148
2 -3.437 u_hpram_top/u_hpram_top_0/u_dll/CLKIN u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[7]/D clk_x2:[R] clk_x1:[R] 5.000 0.005 8.106
3 -3.395 u_hpram_top/u_hpram_top_0/u_dll/CLKIN u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[6]/D clk_x2:[R] clk_x1:[R] 5.000 0.005 8.064
4 -3.352 u_hpram_top/u_hpram_top_0/u_dll/CLKIN u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[5]/D clk_x2:[R] clk_x1:[R] 5.000 0.005 8.021
5 -3.310 u_hpram_top/u_hpram_top_0/u_dll/CLKIN u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[4]/D clk_x2:[R] clk_x1:[R] 5.000 0.005 7.979
6 -3.268 u_hpram_top/u_hpram_top_0/u_dll/CLKIN u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[3]/D clk_x2:[R] clk_x1:[R] 5.000 0.005 7.937
7 -3.226 u_hpram_top/u_hpram_top_0/u_dll/CLKIN u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[2]/D clk_x2:[R] clk_x1:[R] 5.000 0.005 7.895
8 -3.183 u_hpram_top/u_hpram_top_0/u_dll/CLKIN u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[1]/D clk_x2:[R] clk_x1:[R] 5.000 0.005 7.852
9 -0.478 u_hpram_top/u_hpram_top_0/u_dll/CLKIN u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[0]/D clk_x2:[R] clk_x1:[R] 5.000 0.005 5.147
10 1.272 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[8] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4/D3 clk_x1:[R] clk_x1:[R] 10.000 0.000 8.695
11 1.494 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[4] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4/D3 clk_x1:[R] clk_x1:[R] 10.000 0.000 8.473
12 1.509 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[5] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4/D2 clk_x1:[R] clk_x1:[R] 10.000 0.000 8.458
13 1.726 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[10] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4/D1 clk_x1:[R] clk_x1:[R] 10.000 0.000 8.241
14 1.851 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[12] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[2].dq_oser4/D3 clk_x1:[R] clk_x1:[R] 10.000 0.000 8.115
15 2.079 u_test/curr_state.WRITE_ALL_ADDR_s0/Q u_test/addr_add_w_11_s1/CE clk_x1:[R] clk_x1:[R] 10.000 0.000 7.889
16 2.079 u_test/curr_state.WRITE_ALL_ADDR_s0/Q u_test/addr_add_w_18_s1/CE clk_x1:[R] clk_x1:[R] 10.000 0.000 7.889
17 2.346 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[21] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[4].dq_oser4/D2 clk_x1:[R] clk_x1:[R] 10.000 0.000 7.621
18 2.360 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[33] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[7].dq_oser4/D2 clk_x1:[R] clk_x1:[R] 10.000 0.000 7.607
19 2.377 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[29] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[6].dq_oser4/D2 clk_x1:[R] clk_x1:[R] 10.000 0.000 7.590
20 2.383 u_test/curr_state.WRITE_ALL_ADDR_s0/Q u_test/addr_add_w_6_s1/CE clk_x1:[R] clk_x1:[R] 10.000 0.000 7.585
21 2.383 u_test/curr_state.WRITE_ALL_ADDR_s0/Q u_test/addr_add_w_7_s1/CE clk_x1:[R] clk_x1:[R] 10.000 0.000 7.585
22 2.383 u_test/curr_state.WRITE_ALL_ADDR_s0/Q u_test/addr_add_w_9_s1/CE clk_x1:[R] clk_x1:[R] 10.000 0.000 7.585
23 2.383 u_test/curr_state.WRITE_ALL_ADDR_s0/Q u_test/addr_add_w_19_s1/CE clk_x1:[R] clk_x1:[R] 10.000 0.000 7.585
24 2.383 u_test/curr_state.WRITE_ALL_ADDR_s0/Q u_test/addr_add_w_20_s1/CE clk_x1:[R] clk_x1:[R] 10.000 0.000 7.585
25 2.383 u_test/curr_state.WRITE_ALL_ADDR_s0/Q u_test/addr_add_w_21_s1/CE clk_x1:[R] clk_x1:[R] 10.000 0.000 7.585

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.411 u_hpram_top/u_hpram_top_0/u_hpram_init/c_state[9]/Q u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[10]/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.422
2 0.440 u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[0]/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.451
3 0.440 u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[1]/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.451
4 0.440 u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[2]/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.451
5 0.440 u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[3]/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.451
6 0.440 u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[4]/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.451
7 0.440 u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[5]/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.451
8 0.524 u_test/check_data_13_s3/Q u_test/check_data_13_s3/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
9 0.524 u_test/RD_DONE_s8/Q u_test/RD_DONE_s8/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
10 0.524 u_test/WR_CYC_CNT_0_s3/Q u_test/WR_CYC_CNT_0_s3/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
11 0.524 u_test/wr_data_add_3_s1/Q u_test/wr_data_add_3_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
12 0.524 u_test/wr_data_add_7_s1/Q u_test/wr_data_add_7_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
13 0.524 u_test/wr_data_add_27_s1/Q u_test/wr_data_add_27_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
14 0.524 u_test/wr_data_add_29_s1/Q u_test/wr_data_add_29_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
15 0.524 u_test/addr_add_w_17_s1/Q u_test/addr_add_w_17_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
16 0.524 u_test/addr_add_w_21_s1/Q u_test/addr_add_w_21_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
17 0.524 u_test/RD_CYC_CNT_3_s1/Q u_test/RD_CYC_CNT_3_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
18 0.524 u_test/RD_CYC_CNT_14_s1/Q u_test/RD_CYC_CNT_14_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
19 0.524 u_test/RD_CYC_CNT_16_s1/Q u_test/RD_CYC_CNT_16_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
20 0.524 u_test/WR_CYC_CNT_3_s1/Q u_test/WR_CYC_CNT_3_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
21 0.524 u_test/WR_CYC_CNT_12_s1/Q u_test/WR_CYC_CNT_12_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
22 0.524 u_test/WR_CYC_CNT_16_s1/Q u_test/WR_CYC_CNT_16_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
23 0.524 u_test/WR_CNT_4_s1/Q u_test/WR_CNT_4_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
24 0.524 u_test/start_cnt_5_s1/Q u_test/start_cnt_5_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
25 0.524 u_test/addr_add_r_15_s0/Q u_test/addr_add_r_15_s0/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 4.019 4.945 0.926 Low Pulse Width clk_x1 u_hpram_top/u_hpram_top_0/rd_data_valid_d_Z
2 4.019 4.945 0.926 Low Pulse Width clk_x1 u_hpram_top/u_hpram_top_0/rd_data_d_Z[23]
3 4.019 4.945 0.926 Low Pulse Width clk_x1 u_hpram_top/u_hpram_top_0/rd_data_d_Z[15]
4 4.019 4.945 0.926 Low Pulse Width clk_x1 u_hpram_top/u_hpram_top_0/rd_data_d_Z[11]
5 4.019 4.945 0.926 Low Pulse Width clk_x1 u_hpram_top/u_hpram_top_0/rd_data_d_Z[30]
6 4.019 4.945 0.926 Low Pulse Width clk_x1 u_hpram_top/u_hpram_top_0/rd_data_d_Z[29]
7 4.019 4.945 0.926 Low Pulse Width clk_x1 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/d2_Z[2]
8 4.019 4.945 0.926 Low Pulse Width clk_x1 u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/CA_Z[43]
9 4.019 4.945 0.926 Low Pulse Width clk_x1 u_test/WR_CYC_CNT_14_s1
10 4.019 4.945 0.926 Low Pulse Width clk_x1 u_test/WR_CYC_CNT_15_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -3.479
Data Arrival Time 13.332
Data Required Time 9.853
From u_hpram_top/u_hpram_top_0/u_dll
To u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[8]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 1 PLL_L pllvr_inst/CLKOUT
5.000 0.000 tNET RR 3 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKIN
5.184 0.184 tINS RR 22 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKOUT
5.269 0.085 tNET RR 8 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/CLKIN
5.689 0.420 tINS RF 2 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/STEP[0]
8.694 3.005 tNET FF 2 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/I0
9.404 0.710 tINS FF 1 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/COUT
9.404 0.000 tNET FF 2 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/CIN
9.446 0.042 tINS FF 1 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/COUT
9.446 0.000 tNET FF 2 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/CIN
9.488 0.042 tINS FF 1 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/COUT
9.488 0.000 tNET FF 2 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/CIN
9.530 0.042 tINS FF 1 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/COUT
9.530 0.000 tNET FF 2 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/CIN
9.573 0.042 tINS FF 1 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/COUT
9.573 0.000 tNET FF 2 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/CIN
9.615 0.042 tINS FF 1 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/COUT
9.615 0.000 tNET FF 2 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/CIN
9.657 0.042 tINS FF 1 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/COUT
9.657 0.000 tNET FF 2 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/CIN
9.699 0.042 tINS FF 1 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/COUT
10.725 1.025 tNET FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/I1
11.489 0.765 tINS FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/F
12.212 0.722 tNET FF 2 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/I1
12.619 0.408 tINS FR 1 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/COUT
12.619 0.000 tNET RR 2 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/CIN
12.661 0.042 tINS RF 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/COUT
12.661 0.000 tNET FF 2 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/CIN
12.704 0.042 tINS FF 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/COUT
12.704 0.000 tNET FF 2 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/CIN
12.746 0.042 tINS FF 1 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/COUT
12.746 0.000 tNET FF 2 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/CIN
12.788 0.042 tINS FF 1 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/COUT
12.788 0.000 tNET FF 2 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_5_0/CIN
12.830 0.042 tINS FF 1 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_5_0/COUT
12.830 0.000 tNET FF 2 R15C13[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_6_0/CIN
12.873 0.042 tINS FF 1 R15C13[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_6_0/COUT
12.873 0.000 tNET FF 2 R15C13[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_7_0/CIN
12.915 0.042 tINS FF 1 R15C13[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_7_0/COUT
12.915 0.000 tNET FF 2 R15C13[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_s_8_0/CIN
13.332 0.417 tINS FF 1 R15C13[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_s_8_0/SUM
13.332 0.000 tNET FF 1 R15C13[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[8]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R15C13[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[8]/CLK
10.149 -0.030 tUnc u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[8]
9.853 -0.296 tSu 1 R15C13[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[8]

Path Statistics:

Clock Skew -0.005
Setup Relationship 5.000
Logic Level 8
Arrival Clock Path Delay cell: 0.184, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 3.310, 40.626%; route: 4.753, 58.329%; tC2Q: 0.085, 1.045%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path2

Path Summary:

Slack -3.437
Data Arrival Time 13.290
Data Required Time 9.853
From u_hpram_top/u_hpram_top_0/u_dll
To u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[7]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 1 PLL_L pllvr_inst/CLKOUT
5.000 0.000 tNET RR 3 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKIN
5.184 0.184 tINS RR 22 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKOUT
5.269 0.085 tNET RR 8 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/CLKIN
5.689 0.420 tINS RF 2 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/STEP[0]
8.694 3.005 tNET FF 2 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/I0
9.404 0.710 tINS FF 1 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/COUT
9.404 0.000 tNET FF 2 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/CIN
9.446 0.042 tINS FF 1 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/COUT
9.446 0.000 tNET FF 2 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/CIN
9.488 0.042 tINS FF 1 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/COUT
9.488 0.000 tNET FF 2 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/CIN
9.530 0.042 tINS FF 1 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/COUT
9.530 0.000 tNET FF 2 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/CIN
9.573 0.042 tINS FF 1 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/COUT
9.573 0.000 tNET FF 2 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/CIN
9.615 0.042 tINS FF 1 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/COUT
9.615 0.000 tNET FF 2 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/CIN
9.657 0.042 tINS FF 1 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/COUT
9.657 0.000 tNET FF 2 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/CIN
9.699 0.042 tINS FF 1 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/COUT
10.725 1.025 tNET FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/I1
11.489 0.765 tINS FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/F
12.212 0.722 tNET FF 2 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/I1
12.619 0.408 tINS FR 1 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/COUT
12.619 0.000 tNET RR 2 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/CIN
12.661 0.042 tINS RF 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/COUT
12.661 0.000 tNET FF 2 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/CIN
12.704 0.042 tINS FF 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/COUT
12.704 0.000 tNET FF 2 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/CIN
12.746 0.042 tINS FF 1 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/COUT
12.746 0.000 tNET FF 2 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/CIN
12.788 0.042 tINS FF 1 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/COUT
12.788 0.000 tNET FF 2 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_5_0/CIN
12.830 0.042 tINS FF 1 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_5_0/COUT
12.830 0.000 tNET FF 2 R15C13[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_6_0/CIN
12.873 0.042 tINS FF 1 R15C13[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_6_0/COUT
12.873 0.000 tNET FF 2 R15C13[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_7_0/CIN
13.290 0.417 tINS FF 1 R15C13[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_7_0/SUM
13.290 0.000 tNET FF 1 R15C13[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[7]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R15C13[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[7]/CLK
10.149 -0.030 tUnc u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[7]
9.853 -0.296 tSu 1 R15C13[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[7]

Path Statistics:

Clock Skew -0.005
Setup Relationship 5.000
Logic Level 8
Arrival Clock Path Delay cell: 0.184, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 3.268, 40.317%; route: 4.753, 58.633%; tC2Q: 0.085, 1.051%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path3

Path Summary:

Slack -3.395
Data Arrival Time 13.247
Data Required Time 9.853
From u_hpram_top/u_hpram_top_0/u_dll
To u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[6]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 1 PLL_L pllvr_inst/CLKOUT
5.000 0.000 tNET RR 3 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKIN
5.184 0.184 tINS RR 22 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKOUT
5.269 0.085 tNET RR 8 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/CLKIN
5.689 0.420 tINS RF 2 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/STEP[0]
8.694 3.005 tNET FF 2 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/I0
9.404 0.710 tINS FF 1 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/COUT
9.404 0.000 tNET FF 2 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/CIN
9.446 0.042 tINS FF 1 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/COUT
9.446 0.000 tNET FF 2 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/CIN
9.488 0.042 tINS FF 1 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/COUT
9.488 0.000 tNET FF 2 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/CIN
9.530 0.042 tINS FF 1 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/COUT
9.530 0.000 tNET FF 2 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/CIN
9.573 0.042 tINS FF 1 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/COUT
9.573 0.000 tNET FF 2 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/CIN
9.615 0.042 tINS FF 1 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/COUT
9.615 0.000 tNET FF 2 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/CIN
9.657 0.042 tINS FF 1 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/COUT
9.657 0.000 tNET FF 2 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/CIN
9.699 0.042 tINS FF 1 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/COUT
10.725 1.025 tNET FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/I1
11.489 0.765 tINS FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/F
12.212 0.722 tNET FF 2 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/I1
12.619 0.408 tINS FR 1 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/COUT
12.619 0.000 tNET RR 2 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/CIN
12.661 0.042 tINS RF 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/COUT
12.661 0.000 tNET FF 2 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/CIN
12.704 0.042 tINS FF 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/COUT
12.704 0.000 tNET FF 2 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/CIN
12.746 0.042 tINS FF 1 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/COUT
12.746 0.000 tNET FF 2 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/CIN
12.788 0.042 tINS FF 1 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/COUT
12.788 0.000 tNET FF 2 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_5_0/CIN
12.830 0.042 tINS FF 1 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_5_0/COUT
12.830 0.000 tNET FF 2 R15C13[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_6_0/CIN
13.247 0.417 tINS FF 1 R15C13[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_6_0/SUM
13.247 0.000 tNET FF 1 R15C13[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[6]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R15C13[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[6]/CLK
10.149 -0.030 tUnc u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[6]
9.853 -0.296 tSu 1 R15C13[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[6]

Path Statistics:

Clock Skew -0.005
Setup Relationship 5.000
Logic Level 8
Arrival Clock Path Delay cell: 0.184, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 3.226, 40.004%; route: 4.753, 58.940%; tC2Q: 0.085, 1.056%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path4

Path Summary:

Slack -3.352
Data Arrival Time 13.205
Data Required Time 9.853
From u_hpram_top/u_hpram_top_0/u_dll
To u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[5]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 1 PLL_L pllvr_inst/CLKOUT
5.000 0.000 tNET RR 3 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKIN
5.184 0.184 tINS RR 22 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKOUT
5.269 0.085 tNET RR 8 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/CLKIN
5.689 0.420 tINS RF 2 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/STEP[0]
8.694 3.005 tNET FF 2 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/I0
9.404 0.710 tINS FF 1 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/COUT
9.404 0.000 tNET FF 2 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/CIN
9.446 0.042 tINS FF 1 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/COUT
9.446 0.000 tNET FF 2 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/CIN
9.488 0.042 tINS FF 1 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/COUT
9.488 0.000 tNET FF 2 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/CIN
9.530 0.042 tINS FF 1 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/COUT
9.530 0.000 tNET FF 2 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/CIN
9.573 0.042 tINS FF 1 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/COUT
9.573 0.000 tNET FF 2 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/CIN
9.615 0.042 tINS FF 1 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/COUT
9.615 0.000 tNET FF 2 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/CIN
9.657 0.042 tINS FF 1 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/COUT
9.657 0.000 tNET FF 2 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/CIN
9.699 0.042 tINS FF 1 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/COUT
10.725 1.025 tNET FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/I1
11.489 0.765 tINS FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/F
12.212 0.722 tNET FF 2 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/I1
12.619 0.408 tINS FR 1 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/COUT
12.619 0.000 tNET RR 2 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/CIN
12.661 0.042 tINS RF 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/COUT
12.661 0.000 tNET FF 2 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/CIN
12.704 0.042 tINS FF 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/COUT
12.704 0.000 tNET FF 2 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/CIN
12.746 0.042 tINS FF 1 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/COUT
12.746 0.000 tNET FF 2 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/CIN
12.788 0.042 tINS FF 1 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/COUT
12.788 0.000 tNET FF 2 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_5_0/CIN
13.205 0.417 tINS FF 1 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_5_0/SUM
13.205 0.000 tNET FF 1 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[5]/CLK
10.149 -0.030 tUnc u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[5]
9.853 -0.296 tSu 1 R15C13[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[5]

Path Statistics:

Clock Skew -0.005
Setup Relationship 5.000
Logic Level 8
Arrival Clock Path Delay cell: 0.184, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 3.184, 39.688%; route: 4.753, 59.250%; tC2Q: 0.085, 1.062%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path5

Path Summary:

Slack -3.310
Data Arrival Time 13.163
Data Required Time 9.853
From u_hpram_top/u_hpram_top_0/u_dll
To u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[4]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 1 PLL_L pllvr_inst/CLKOUT
5.000 0.000 tNET RR 3 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKIN
5.184 0.184 tINS RR 22 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKOUT
5.269 0.085 tNET RR 8 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/CLKIN
5.689 0.420 tINS RF 2 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/STEP[0]
8.694 3.005 tNET FF 2 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/I0
9.404 0.710 tINS FF 1 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/COUT
9.404 0.000 tNET FF 2 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/CIN
9.446 0.042 tINS FF 1 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/COUT
9.446 0.000 tNET FF 2 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/CIN
9.488 0.042 tINS FF 1 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/COUT
9.488 0.000 tNET FF 2 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/CIN
9.530 0.042 tINS FF 1 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/COUT
9.530 0.000 tNET FF 2 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/CIN
9.573 0.042 tINS FF 1 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/COUT
9.573 0.000 tNET FF 2 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/CIN
9.615 0.042 tINS FF 1 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/COUT
9.615 0.000 tNET FF 2 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/CIN
9.657 0.042 tINS FF 1 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/COUT
9.657 0.000 tNET FF 2 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/CIN
9.699 0.042 tINS FF 1 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/COUT
10.725 1.025 tNET FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/I1
11.489 0.765 tINS FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/F
12.212 0.722 tNET FF 2 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/I1
12.619 0.408 tINS FR 1 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/COUT
12.619 0.000 tNET RR 2 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/CIN
12.661 0.042 tINS RF 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/COUT
12.661 0.000 tNET FF 2 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/CIN
12.704 0.042 tINS FF 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/COUT
12.704 0.000 tNET FF 2 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/CIN
12.746 0.042 tINS FF 1 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/COUT
12.746 0.000 tNET FF 2 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/CIN
13.163 0.417 tINS FF 1 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_4_0/SUM
13.163 0.000 tNET FF 1 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[4]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[4]/CLK
10.149 -0.030 tUnc u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[4]
9.853 -0.296 tSu 1 R15C12[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[4]

Path Statistics:

Clock Skew -0.005
Setup Relationship 5.000
Logic Level 8
Arrival Clock Path Delay cell: 0.184, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 3.141, 39.369%; route: 4.753, 59.564%; tC2Q: 0.085, 1.067%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path6

Path Summary:

Slack -3.268
Data Arrival Time 13.121
Data Required Time 9.853
From u_hpram_top/u_hpram_top_0/u_dll
To u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[3]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 1 PLL_L pllvr_inst/CLKOUT
5.000 0.000 tNET RR 3 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKIN
5.184 0.184 tINS RR 22 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKOUT
5.269 0.085 tNET RR 8 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/CLKIN
5.689 0.420 tINS RF 2 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/STEP[0]
8.694 3.005 tNET FF 2 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/I0
9.404 0.710 tINS FF 1 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/COUT
9.404 0.000 tNET FF 2 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/CIN
9.446 0.042 tINS FF 1 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/COUT
9.446 0.000 tNET FF 2 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/CIN
9.488 0.042 tINS FF 1 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/COUT
9.488 0.000 tNET FF 2 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/CIN
9.530 0.042 tINS FF 1 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/COUT
9.530 0.000 tNET FF 2 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/CIN
9.573 0.042 tINS FF 1 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/COUT
9.573 0.000 tNET FF 2 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/CIN
9.615 0.042 tINS FF 1 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/COUT
9.615 0.000 tNET FF 2 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/CIN
9.657 0.042 tINS FF 1 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/COUT
9.657 0.000 tNET FF 2 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/CIN
9.699 0.042 tINS FF 1 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/COUT
10.725 1.025 tNET FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/I1
11.489 0.765 tINS FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/F
12.212 0.722 tNET FF 2 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/I1
12.619 0.408 tINS FR 1 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/COUT
12.619 0.000 tNET RR 2 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/CIN
12.661 0.042 tINS RF 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/COUT
12.661 0.000 tNET FF 2 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/CIN
12.704 0.042 tINS FF 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/COUT
12.704 0.000 tNET FF 2 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/CIN
13.121 0.417 tINS FF 1 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_3_0/SUM
13.121 0.000 tNET FF 1 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[3]/CLK
10.149 -0.030 tUnc u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[3]
9.853 -0.296 tSu 1 R15C12[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[3]

Path Statistics:

Clock Skew -0.005
Setup Relationship 5.000
Logic Level 8
Arrival Clock Path Delay cell: 0.184, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 3.099, 39.046%; route: 4.753, 59.881%; tC2Q: 0.085, 1.073%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path7

Path Summary:

Slack -3.226
Data Arrival Time 13.079
Data Required Time 9.853
From u_hpram_top/u_hpram_top_0/u_dll
To u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[2]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 1 PLL_L pllvr_inst/CLKOUT
5.000 0.000 tNET RR 3 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKIN
5.184 0.184 tINS RR 22 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKOUT
5.269 0.085 tNET RR 8 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/CLKIN
5.689 0.420 tINS RF 2 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/STEP[0]
8.694 3.005 tNET FF 2 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/I0
9.404 0.710 tINS FF 1 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/COUT
9.404 0.000 tNET FF 2 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/CIN
9.446 0.042 tINS FF 1 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/COUT
9.446 0.000 tNET FF 2 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/CIN
9.488 0.042 tINS FF 1 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/COUT
9.488 0.000 tNET FF 2 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/CIN
9.530 0.042 tINS FF 1 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/COUT
9.530 0.000 tNET FF 2 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/CIN
9.573 0.042 tINS FF 1 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/COUT
9.573 0.000 tNET FF 2 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/CIN
9.615 0.042 tINS FF 1 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/COUT
9.615 0.000 tNET FF 2 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/CIN
9.657 0.042 tINS FF 1 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/COUT
9.657 0.000 tNET FF 2 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/CIN
9.699 0.042 tINS FF 1 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/COUT
10.725 1.025 tNET FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/I1
11.489 0.765 tINS FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/F
12.212 0.722 tNET FF 2 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/I1
12.619 0.408 tINS FR 1 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/COUT
12.619 0.000 tNET RR 2 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/CIN
12.661 0.042 tINS RF 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/COUT
12.661 0.000 tNET FF 2 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/CIN
13.079 0.417 tINS FF 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_2_0/SUM
13.079 0.000 tNET FF 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[2]/CLK
10.149 -0.030 tUnc u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[2]
9.853 -0.296 tSu 1 R15C12[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[2]

Path Statistics:

Clock Skew -0.005
Setup Relationship 5.000
Logic Level 8
Arrival Clock Path Delay cell: 0.184, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 3.057, 38.720%; route: 4.753, 60.201%; tC2Q: 0.085, 1.079%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path8

Path Summary:

Slack -3.183
Data Arrival Time 13.036
Data Required Time 9.853
From u_hpram_top/u_hpram_top_0/u_dll
To u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[1]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 1 PLL_L pllvr_inst/CLKOUT
5.000 0.000 tNET RR 3 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKIN
5.184 0.184 tINS RR 22 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKOUT
5.269 0.085 tNET RR 8 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/CLKIN
5.689 0.420 tINS RF 2 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/STEP[0]
8.694 3.005 tNET FF 2 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/I0
9.404 0.710 tINS FF 1 R15C5[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_1_0/COUT
9.404 0.000 tNET FF 2 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/CIN
9.446 0.042 tINS FF 1 R15C5[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_2_0/COUT
9.446 0.000 tNET FF 2 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/CIN
9.488 0.042 tINS FF 1 R15C5[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_3_0/COUT
9.488 0.000 tNET FF 2 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/CIN
9.530 0.042 tINS FF 1 R15C5[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_4_0/COUT
9.530 0.000 tNET FF 2 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/CIN
9.573 0.042 tINS FF 1 R15C5[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_5_0/COUT
9.573 0.000 tNET FF 2 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/CIN
9.615 0.042 tINS FF 1 R15C6[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_6_0/COUT
9.615 0.000 tNET FF 2 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/CIN
9.657 0.042 tINS FF 1 R15C6[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_7_0/COUT
9.657 0.000 tNET FF 2 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/CIN
9.699 0.042 tINS FF 1 R15C6[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_cry_8_0/COUT
10.725 1.025 tNET FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/I1
11.489 0.765 tINS FF 1 R15C8[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step8_cZ/F
12.212 0.722 tNET FF 2 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/I1
12.619 0.408 tINS FR 1 R15C12[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_0_0/COUT
12.619 0.000 tNET RR 2 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/CIN
13.036 0.417 tINS RF 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_3_cry_1_0/SUM
13.036 0.000 tNET FF 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[1]/CLK
10.149 -0.030 tUnc u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[1]
9.853 -0.296 tSu 1 R15C12[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[1]

Path Statistics:

Clock Skew -0.005
Setup Relationship 5.000
Logic Level 8
Arrival Clock Path Delay cell: 0.184, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 3.015, 38.390%; route: 4.753, 60.525%; tC2Q: 0.085, 1.085%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path9

Path Summary:

Slack -0.478
Data Arrival Time 10.331
Data Required Time 9.853
From u_hpram_top/u_hpram_top_0/u_dll
To u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[0]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 1 PLL_L pllvr_inst/CLKOUT
5.000 0.000 tNET RR 3 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKIN
5.184 0.184 tINS RR 22 - u_hpram_top/u_hpram_top_0/u_dqce_clk_x2p/CLKOUT
5.269 0.085 tNET RR 8 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/CLKIN
5.689 0.420 tINS RF 2 DLL_BL u_hpram_top/u_hpram_top_0/u_dll/STEP[3]
8.217 2.528 tNET FF 2 R15C18[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_4_0/I0
8.927 0.710 tINS FF 1 R15C18[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_4_0/COUT
8.927 0.000 tNET FF 2 R15C18[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_5_0/CIN
8.969 0.042 tINS FF 1 R15C18[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_5_0/COUT
8.969 0.000 tNET FF 2 R15C19[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_6_0/CIN
9.011 0.042 tINS FF 1 R15C19[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_6_0/COUT
9.011 0.000 tNET FF 2 R15C19[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_7_0/CIN
9.054 0.042 tINS FF 1 R15C19[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_7_0/COUT
9.054 0.000 tNET FF 2 R15C19[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_8_0/CIN
9.096 0.042 tINS FF 1 R15C19[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/un1_step_1_cry_8_0/COUT
9.517 0.421 tNET FF 1 R15C19[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_1_3/I2
10.331 0.814 tINS FF 1 R15C19[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_1_3/F
10.331 0.000 tNET FF 1 R15C19[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R15C19[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[0]/CLK
10.149 -0.030 tUnc u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[0]
9.853 -0.296 tSu 1 R15C19[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/step_Z[0]

Path Statistics:

Clock Skew -0.005
Setup Relationship 5.000
Logic Level 5
Arrival Clock Path Delay cell: 0.184, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 2.113, 41.045%; route: 2.950, 57.300%; tC2Q: 0.085, 1.655%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path10

Path Summary:

Slack 1.272
Data Arrival Time 8.874
Data Required Time 10.146
From u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0
To u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 36 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/CLKB
2.743 2.564 tC2Q RF 1 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[8]
4.534 1.791 tNET FF 1 R11C21[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/data_mask_d_G_7/I0
5.299 0.765 tINS FF 1 R11C21[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/data_mask_d_G_7/F
5.895 0.596 tNET FF 1 R14C21[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[4]/I3
6.709 0.814 tINS FF 1 R14C21[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[4]/F
8.874 2.165 tNET FF 1 IOB7[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 IOB7[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4/PCLK
10.146 -0.033 tSu 1 IOB7[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 1.579, 18.161%; route: 4.552, 52.353%; tC2Q: 2.564, 29.487%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path11

Path Summary:

Slack 1.494
Data Arrival Time 8.652
Data Required Time 10.146
From u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0
To u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 36 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/CLKB
2.743 2.564 tC2Q RF 1 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[4]
4.782 2.039 tNET FF 1 R9C24[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[0]/I0
5.597 0.814 tINS FF 1 R9C24[2][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[0]/F
5.601 0.004 tNET FF 1 R9C24[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[0]/I1
6.365 0.765 tINS FF 1 R9C24[2][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[0]/F
8.652 2.287 tNET FF 1 IOB7[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 IOB7[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4/PCLK
10.146 -0.033 tSu 1 IOB7[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 1.579, 18.636%; route: 4.330, 51.105%; tC2Q: 2.564, 30.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path12

Path Summary:

Slack 1.509
Data Arrival Time 8.637
Data Required Time 10.146
From u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0
To u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 36 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/CLKB
2.743 2.564 tC2Q RF 1 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[5]
4.782 2.039 tNET FF 1 R9C24[3][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[1]/I0
5.597 0.814 tINS FF 1 R9C24[3][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[1]/F
5.601 0.004 tNET FF 1 R9C24[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[1]/I1
6.365 0.765 tINS FF 1 R9C24[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[1]/F
8.637 2.272 tNET FF 1 IOB7[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 IOB7[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4/PCLK
10.146 -0.033 tSu 1 IOB7[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[0].dq_oser4

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 1.579, 18.670%; route: 4.315, 51.017%; tC2Q: 2.564, 30.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path13

Path Summary:

Slack 1.726
Data Arrival Time 8.420
Data Required Time 10.146
From u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0
To u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 36 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/CLKB
2.743 2.564 tC2Q RF 1 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[10]
4.908 2.165 tNET FF 1 R11C24[3][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/data_mask_d_G_9/I0
5.695 0.786 tINS FR 1 R11C24[3][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/data_mask_d_G_9/F
6.005 0.310 tNET RR 1 R12C24[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[6]/I3
6.614 0.609 tINS RF 1 R12C24[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[6]/F
8.420 1.806 tNET FF 1 IOB7[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 IOB7[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4/PCLK
10.146 -0.033 tSu 1 IOB7[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[1].dq_oser4

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 1.395, 16.932%; route: 4.282, 51.957%; tC2Q: 2.564, 31.112%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path14

Path Summary:

Slack 1.851
Data Arrival Time 8.295
Data Required Time 10.146
From u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0
To u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[2].dq_oser4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 36 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/CLKB
2.743 2.564 tC2Q RF 1 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[12]
4.660 1.917 tNET FF 1 R9C24[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[8]/I0
5.425 0.765 tINS FF 1 R9C24[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[8]/F
5.429 0.004 tNET FF 1 R9C24[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[8]/I1
6.243 0.814 tINS FF 1 R9C24[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[8]/F
8.295 2.051 tNET FF 1 IOB14[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[2].dq_oser4/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 IOB14[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[2].dq_oser4/PCLK
10.146 -0.033 tSu 1 IOB14[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[2].dq_oser4

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 1.579, 19.458%; route: 3.972, 48.949%; tC2Q: 2.564, 31.593%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path15

Path Summary:

Slack 2.079
Data Arrival Time 8.068
Data Required Time 10.147
From u_test/curr_state.WRITE_ALL_ADDR_s0
To u_test/addr_add_w_11_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 1 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/CLK
0.519 0.340 tC2Q RF 69 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/Q
1.996 1.477 tNET FF 1 R11C27[3][A] u_test/n443_s2/I1
2.760 0.765 tINS FF 24 R11C27[3][A] u_test/n443_s2/F
4.007 1.247 tNET FF 1 R7C31[3][B] u_test/n443_s0/I3
4.471 0.464 tINS FF 35 R7C31[3][B] u_test/n443_s0/F
6.442 1.971 tNET FF 1 R12C29[2][B] u_test/addr_add_w_21_s3/I3
7.228 0.786 tINS FR 16 R12C29[2][B] u_test/addr_add_w_21_s3/F
8.068 0.840 tNET RR 1 R13C29[1][A] u_test/addr_add_w_11_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R13C29[1][A] u_test/addr_add_w_11_s1/CLK
10.147 -0.032 tSu 1 R13C29[1][A] u_test/addr_add_w_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 2.015, 25.540%; route: 5.534, 70.155%; tC2Q: 0.340, 4.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path16

Path Summary:

Slack 2.079
Data Arrival Time 8.068
Data Required Time 10.147
From u_test/curr_state.WRITE_ALL_ADDR_s0
To u_test/addr_add_w_18_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 1 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/CLK
0.519 0.340 tC2Q RF 69 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/Q
1.996 1.477 tNET FF 1 R11C27[3][A] u_test/n443_s2/I1
2.760 0.765 tINS FF 24 R11C27[3][A] u_test/n443_s2/F
4.007 1.247 tNET FF 1 R7C31[3][B] u_test/n443_s0/I3
4.471 0.464 tINS FF 35 R7C31[3][B] u_test/n443_s0/F
6.442 1.971 tNET FF 1 R12C29[2][B] u_test/addr_add_w_21_s3/I3
7.228 0.786 tINS FR 16 R12C29[2][B] u_test/addr_add_w_21_s3/F
8.068 0.840 tNET RR 1 R13C29[0][B] u_test/addr_add_w_18_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R13C29[0][B] u_test/addr_add_w_18_s1/CLK
10.147 -0.032 tSu 1 R13C29[0][B] u_test/addr_add_w_18_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 2.015, 25.540%; route: 5.534, 70.155%; tC2Q: 0.340, 4.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path17

Path Summary:

Slack 2.346
Data Arrival Time 7.800
Data Required Time 10.146
From u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0
To u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[4].dq_oser4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 36 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/CLKB
2.743 2.564 tC2Q RF 1 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[21]
4.781 2.038 tNET FF 1 R14C21[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[17]/I0
5.546 0.765 tINS FF 1 R14C21[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[17]/F
5.550 0.004 tNET FF 1 R14C21[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[17]/I1
6.364 0.814 tINS FF 1 R14C21[1][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[17]/F
7.800 1.436 tNET FF 1 IOB24[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[4].dq_oser4/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 IOB24[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[4].dq_oser4/PCLK
10.146 -0.033 tSu 1 IOB24[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[4].dq_oser4

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 1.579, 20.720%; route: 3.478, 45.638%; tC2Q: 2.564, 33.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path18

Path Summary:

Slack 2.360
Data Arrival Time 7.786
Data Required Time 10.146
From u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0
To u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[7].dq_oser4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 36 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/CLKB
2.743 2.564 tC2Q RF 1 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[33]
4.548 1.805 tNET FF 1 R9C24[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[29]/I0
5.309 0.760 tINS FR 1 R9C24[1][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[29]/F
5.619 0.310 tNET RR 1 R9C25[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[29]/I1
6.228 0.609 tINS RF 1 R9C25[0][B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[29]/F
7.786 1.558 tNET FF 1 IOB29[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[7].dq_oser4/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 IOB29[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[7].dq_oser4/PCLK
10.146 -0.033 tSu 1 IOB29[A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[7].dq_oser4

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 1.369, 18.002%; route: 3.673, 48.293%; tC2Q: 2.564, 33.705%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path19

Path Summary:

Slack 2.377
Data Arrival Time 7.769
Data Required Time 10.146
From u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0
To u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[6].dq_oser4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 36 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/CLKB
2.743 2.564 tC2Q RF 1 BSRAM_R10[0] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_mask_mem_mask_0_0/DO[29]
4.781 2.038 tNET FF 1 R9C24[3][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[25]/I0
5.567 0.786 tINS FR 1 R9C24[3][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_0[25]/F
5.878 0.310 tNET RR 1 R9C25[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[25]/I1
6.692 0.814 tINS RF 1 R9C25[0][A] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/wr_dq_1_cZ[25]/F
7.769 1.077 tNET FF 1 IOB25[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[6].dq_oser4/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 IOB25[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[6].dq_oser4/PCLK
10.146 -0.033 tSu 1 IOB25[B] u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/oserdes_data_gen[6].dq_oser4

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 1.601, 21.088%; route: 3.425, 45.131%; tC2Q: 2.564, 33.780%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path20

Path Summary:

Slack 2.383
Data Arrival Time 7.765
Data Required Time 10.147
From u_test/curr_state.WRITE_ALL_ADDR_s0
To u_test/addr_add_w_6_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 1 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/CLK
0.519 0.340 tC2Q RF 69 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/Q
1.996 1.477 tNET FF 1 R11C27[3][A] u_test/n443_s2/I1
2.760 0.765 tINS FF 24 R11C27[3][A] u_test/n443_s2/F
4.007 1.247 tNET FF 1 R7C31[3][B] u_test/n443_s0/I3
4.471 0.464 tINS FF 35 R7C31[3][B] u_test/n443_s0/F
6.442 1.971 tNET FF 1 R12C29[2][B] u_test/addr_add_w_21_s3/I3
7.228 0.786 tINS FR 16 R12C29[2][B] u_test/addr_add_w_21_s3/F
7.765 0.537 tNET RR 1 R12C31[1][B] u_test/addr_add_w_6_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R12C31[1][B] u_test/addr_add_w_6_s1/CLK
10.147 -0.032 tSu 1 R12C31[1][B] u_test/addr_add_w_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 2.015, 26.562%; route: 5.231, 68.961%; tC2Q: 0.340, 4.477%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path21

Path Summary:

Slack 2.383
Data Arrival Time 7.765
Data Required Time 10.147
From u_test/curr_state.WRITE_ALL_ADDR_s0
To u_test/addr_add_w_7_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 1 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/CLK
0.519 0.340 tC2Q RF 69 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/Q
1.996 1.477 tNET FF 1 R11C27[3][A] u_test/n443_s2/I1
2.760 0.765 tINS FF 24 R11C27[3][A] u_test/n443_s2/F
4.007 1.247 tNET FF 1 R7C31[3][B] u_test/n443_s0/I3
4.471 0.464 tINS FF 35 R7C31[3][B] u_test/n443_s0/F
6.442 1.971 tNET FF 1 R12C29[2][B] u_test/addr_add_w_21_s3/I3
7.228 0.786 tINS FR 16 R12C29[2][B] u_test/addr_add_w_21_s3/F
7.765 0.537 tNET RR 1 R12C31[2][A] u_test/addr_add_w_7_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R12C31[2][A] u_test/addr_add_w_7_s1/CLK
10.147 -0.032 tSu 1 R12C31[2][A] u_test/addr_add_w_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 2.015, 26.562%; route: 5.231, 68.961%; tC2Q: 0.340, 4.477%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path22

Path Summary:

Slack 2.383
Data Arrival Time 7.765
Data Required Time 10.147
From u_test/curr_state.WRITE_ALL_ADDR_s0
To u_test/addr_add_w_9_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 1 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/CLK
0.519 0.340 tC2Q RF 69 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/Q
1.996 1.477 tNET FF 1 R11C27[3][A] u_test/n443_s2/I1
2.760 0.765 tINS FF 24 R11C27[3][A] u_test/n443_s2/F
4.007 1.247 tNET FF 1 R7C31[3][B] u_test/n443_s0/I3
4.471 0.464 tINS FF 35 R7C31[3][B] u_test/n443_s0/F
6.442 1.971 tNET FF 1 R12C29[2][B] u_test/addr_add_w_21_s3/I3
7.228 0.786 tINS FR 16 R12C29[2][B] u_test/addr_add_w_21_s3/F
7.765 0.537 tNET RR 1 R12C31[2][B] u_test/addr_add_w_9_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R12C31[2][B] u_test/addr_add_w_9_s1/CLK
10.147 -0.032 tSu 1 R12C31[2][B] u_test/addr_add_w_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 2.015, 26.562%; route: 5.231, 68.961%; tC2Q: 0.340, 4.477%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path23

Path Summary:

Slack 2.383
Data Arrival Time 7.765
Data Required Time 10.147
From u_test/curr_state.WRITE_ALL_ADDR_s0
To u_test/addr_add_w_19_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 1 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/CLK
0.519 0.340 tC2Q RF 69 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/Q
1.996 1.477 tNET FF 1 R11C27[3][A] u_test/n443_s2/I1
2.760 0.765 tINS FF 24 R11C27[3][A] u_test/n443_s2/F
4.007 1.247 tNET FF 1 R7C31[3][B] u_test/n443_s0/I3
4.471 0.464 tINS FF 35 R7C31[3][B] u_test/n443_s0/F
6.442 1.971 tNET FF 1 R12C29[2][B] u_test/addr_add_w_21_s3/I3
7.228 0.786 tINS FR 16 R12C29[2][B] u_test/addr_add_w_21_s3/F
7.765 0.537 tNET RR 1 R12C31[0][A] u_test/addr_add_w_19_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R12C31[0][A] u_test/addr_add_w_19_s1/CLK
10.147 -0.032 tSu 1 R12C31[0][A] u_test/addr_add_w_19_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 2.015, 26.562%; route: 5.231, 68.961%; tC2Q: 0.340, 4.477%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path24

Path Summary:

Slack 2.383
Data Arrival Time 7.765
Data Required Time 10.147
From u_test/curr_state.WRITE_ALL_ADDR_s0
To u_test/addr_add_w_20_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 1 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/CLK
0.519 0.340 tC2Q RF 69 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/Q
1.996 1.477 tNET FF 1 R11C27[3][A] u_test/n443_s2/I1
2.760 0.765 tINS FF 24 R11C27[3][A] u_test/n443_s2/F
4.007 1.247 tNET FF 1 R7C31[3][B] u_test/n443_s0/I3
4.471 0.464 tINS FF 35 R7C31[3][B] u_test/n443_s0/F
6.442 1.971 tNET FF 1 R12C29[2][B] u_test/addr_add_w_21_s3/I3
7.228 0.786 tINS FR 16 R12C29[2][B] u_test/addr_add_w_21_s3/F
7.765 0.537 tNET RR 1 R12C31[0][B] u_test/addr_add_w_20_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R12C31[0][B] u_test/addr_add_w_20_s1/CLK
10.147 -0.032 tSu 1 R12C31[0][B] u_test/addr_add_w_20_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 2.015, 26.562%; route: 5.231, 68.961%; tC2Q: 0.340, 4.477%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Path25

Path Summary:

Slack 2.383
Data Arrival Time 7.765
Data Required Time 10.147
From u_test/curr_state.WRITE_ALL_ADDR_s0
To u_test/addr_add_w_21_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179 0.179 tNET RR 1 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/CLK
0.519 0.340 tC2Q RF 69 R12C27[0][A] u_test/curr_state.WRITE_ALL_ADDR_s0/Q
1.996 1.477 tNET FF 1 R11C27[3][A] u_test/n443_s2/I1
2.760 0.765 tINS FF 24 R11C27[3][A] u_test/n443_s2/F
4.007 1.247 tNET FF 1 R7C31[3][B] u_test/n443_s0/I3
4.471 0.464 tINS FF 35 R7C31[3][B] u_test/n443_s0/F
6.442 1.971 tNET FF 1 R12C29[2][B] u_test/addr_add_w_21_s3/I3
7.228 0.786 tINS FR 16 R12C29[2][B] u_test/addr_add_w_21_s3/F
7.765 0.537 tNET RR 1 R12C31[1][A] u_test/addr_add_w_21_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179 0.179 tNET RR 1 R12C31[1][A] u_test/addr_add_w_21_s1/CLK
10.147 -0.032 tSu 1 R12C31[1][A] u_test/addr_add_w_21_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay cell: 2.015, 26.562%; route: 5.231, 68.961%; tC2Q: 0.340, 4.477%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.179, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.411
Data Arrival Time 0.558
Data Required Time 0.147
From u_hpram_top/u_hpram_top_0/u_hpram_init/c_state[9]
To u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[10]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C14[0][A] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state[9]/CLK
0.383 0.247 tC2Q RR 1 R9C14[0][A] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state[9]/Q
0.558 0.175 tNET RR 1 R9C14[2][A] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[10]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C14[2][A] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[10]/CLK
0.147 0.011 tHld 1 R9C14[2][A] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[10]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path2

Path Summary:

Slack 0.440
Data Arrival Time 0.586
Data Required Time 0.147
From u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]
To u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[0]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/CLK
0.383 0.247 tC2Q RR 8 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q
0.586 0.204 tNET RR 1 R13C16[0][A] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[0]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R13C16[0][A] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[0]/CLK
0.147 0.011 tHld 1 R13C16[0][A] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 45.187%; tC2Q: 0.247, 54.813%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path3

Path Summary:

Slack 0.440
Data Arrival Time 0.586
Data Required Time 0.147
From u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]
To u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[1]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/CLK
0.383 0.247 tC2Q RR 8 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q
0.586 0.204 tNET RR 1 R13C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[1]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R13C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[1]/CLK
0.147 0.011 tHld 1 R13C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 45.187%; tC2Q: 0.247, 54.813%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path4

Path Summary:

Slack 0.440
Data Arrival Time 0.586
Data Required Time 0.147
From u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]
To u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[2]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/CLK
0.383 0.247 tC2Q RR 8 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q
0.586 0.204 tNET RR 1 R13C16[1][A] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[2]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R13C16[1][A] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[2]/CLK
0.147 0.011 tHld 1 R13C16[1][A] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 45.187%; tC2Q: 0.247, 54.813%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path5

Path Summary:

Slack 0.440
Data Arrival Time 0.586
Data Required Time 0.147
From u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]
To u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[3]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/CLK
0.383 0.247 tC2Q RR 8 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q
0.586 0.204 tNET RR 1 R13C16[1][B] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[3]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R13C16[1][B] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[3]/CLK
0.147 0.011 tHld 1 R13C16[1][B] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 45.187%; tC2Q: 0.247, 54.813%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path6

Path Summary:

Slack 0.440
Data Arrival Time 0.586
Data Required Time 0.147
From u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]
To u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[4]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/CLK
0.383 0.247 tC2Q RR 8 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q
0.586 0.204 tNET RR 1 R13C16[2][A] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[4]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R13C16[2][A] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[4]/CLK
0.147 0.011 tHld 1 R13C16[2][A] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 45.187%; tC2Q: 0.247, 54.813%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path7

Path Summary:

Slack 0.440
Data Arrival Time 0.586
Data Required Time 0.147
From u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]
To u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[5]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/CLK
0.383 0.247 tC2Q RR 8 R11C16[0][B] u_hpram_top/u_hpram_top_0/u_hpram_init/c_state_Z[2]/Q
0.586 0.204 tNET RR 1 R13C16[2][B] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[5]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R13C16[2][B] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[5]/CLK
0.147 0.011 tHld 1 R13C16[2][B] u_hpram_top/u_hpram_top_0/u_hpram_init/timer_cnt_Z[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 45.187%; tC2Q: 0.247, 54.813%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path8

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/check_data_13_s3
To u_test/check_data_13_s3
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C26[0][A] u_test/check_data_13_s3/CLK
0.383 0.247 tC2Q RR 3 R9C26[0][A] u_test/check_data_13_s3/Q
0.384 0.002 tNET RR 1 R9C26[0][A] u_test/n1190_s4/I1
0.660 0.276 tINS RF 1 R9C26[0][A] u_test/n1190_s4/F
0.660 0.000 tNET FF 1 R9C26[0][A] u_test/check_data_13_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C26[0][A] u_test/check_data_13_s3/CLK
0.136 0.000 tHld 1 R9C26[0][A] u_test/check_data_13_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path9

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/RD_DONE_s8
To u_test/RD_DONE_s8
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C32[1][A] u_test/RD_DONE_s8/CLK
0.383 0.247 tC2Q RR 2 R11C32[1][A] u_test/RD_DONE_s8/Q
0.384 0.002 tNET RR 1 R11C32[1][A] u_test/n286_s7/I1
0.660 0.276 tINS RF 1 R11C32[1][A] u_test/n286_s7/F
0.660 0.000 tNET FF 1 R11C32[1][A] u_test/RD_DONE_s8/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C32[1][A] u_test/RD_DONE_s8/CLK
0.136 0.000 tHld 1 R11C32[1][A] u_test/RD_DONE_s8

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path10

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/WR_CYC_CNT_0_s3
To u_test/WR_CYC_CNT_0_s3
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R8C31[1][A] u_test/WR_CYC_CNT_0_s3/CLK
0.383 0.247 tC2Q RR 5 R8C31[1][A] u_test/WR_CYC_CNT_0_s3/Q
0.384 0.002 tNET RR 1 R8C31[1][A] u_test/n236_s3/I1
0.660 0.276 tINS RF 1 R8C31[1][A] u_test/n236_s3/F
0.660 0.000 tNET FF 1 R8C31[1][A] u_test/WR_CYC_CNT_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R8C31[1][A] u_test/WR_CYC_CNT_0_s3/CLK
0.136 0.000 tHld 1 R8C31[1][A] u_test/WR_CYC_CNT_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path11

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/wr_data_add_3_s1
To u_test/wr_data_add_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R7C30[1][A] u_test/wr_data_add_3_s1/CLK
0.383 0.247 tC2Q RR 3 R7C30[1][A] u_test/wr_data_add_3_s1/Q
0.384 0.002 tNET RR 1 R7C30[1][A] u_test/n756_s1/I2
0.660 0.276 tINS RF 1 R7C30[1][A] u_test/n756_s1/F
0.660 0.000 tNET FF 1 R7C30[1][A] u_test/wr_data_add_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R7C30[1][A] u_test/wr_data_add_3_s1/CLK
0.136 0.000 tHld 1 R7C30[1][A] u_test/wr_data_add_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path12

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/wr_data_add_7_s1
To u_test/wr_data_add_7_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R6C27[1][A] u_test/wr_data_add_7_s1/CLK
0.383 0.247 tC2Q RR 3 R6C27[1][A] u_test/wr_data_add_7_s1/Q
0.384 0.002 tNET RR 1 R6C27[1][A] u_test/n752_s1/I2
0.660 0.276 tINS RF 1 R6C27[1][A] u_test/n752_s1/F
0.660 0.000 tNET FF 1 R6C27[1][A] u_test/wr_data_add_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R6C27[1][A] u_test/wr_data_add_7_s1/CLK
0.136 0.000 tHld 1 R6C27[1][A] u_test/wr_data_add_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path13

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/wr_data_add_27_s1
To u_test/wr_data_add_27_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R7C29[1][A] u_test/wr_data_add_27_s1/CLK
0.383 0.247 tC2Q RR 3 R7C29[1][A] u_test/wr_data_add_27_s1/Q
0.384 0.002 tNET RR 1 R7C29[1][A] u_test/n732_s1/I2
0.660 0.276 tINS RF 1 R7C29[1][A] u_test/n732_s1/F
0.660 0.000 tNET FF 1 R7C29[1][A] u_test/wr_data_add_27_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R7C29[1][A] u_test/wr_data_add_27_s1/CLK
0.136 0.000 tHld 1 R7C29[1][A] u_test/wr_data_add_27_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path14

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/wr_data_add_29_s1
To u_test/wr_data_add_29_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C29[1][A] u_test/wr_data_add_29_s1/CLK
0.383 0.247 tC2Q RR 3 R11C29[1][A] u_test/wr_data_add_29_s1/Q
0.384 0.002 tNET RR 1 R11C29[1][A] u_test/n730_s1/I2
0.660 0.276 tINS RF 1 R11C29[1][A] u_test/n730_s1/F
0.660 0.000 tNET FF 1 R11C29[1][A] u_test/wr_data_add_29_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C29[1][A] u_test/wr_data_add_29_s1/CLK
0.136 0.000 tHld 1 R11C29[1][A] u_test/wr_data_add_29_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path15

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/addr_add_w_17_s1
To u_test/addr_add_w_17_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R12C28[0][A] u_test/addr_add_w_17_s1/CLK
0.383 0.247 tC2Q RR 4 R12C28[0][A] u_test/addr_add_w_17_s1/Q
0.384 0.002 tNET RR 1 R12C28[0][A] u_test/n819_s1/I0
0.660 0.276 tINS RF 1 R12C28[0][A] u_test/n819_s1/F
0.660 0.000 tNET FF 1 R12C28[0][A] u_test/addr_add_w_17_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R12C28[0][A] u_test/addr_add_w_17_s1/CLK
0.136 0.000 tHld 1 R12C28[0][A] u_test/addr_add_w_17_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path16

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/addr_add_w_21_s1
To u_test/addr_add_w_21_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R12C31[1][A] u_test/addr_add_w_21_s1/CLK
0.383 0.247 tC2Q RR 2 R12C31[1][A] u_test/addr_add_w_21_s1/Q
0.384 0.002 tNET RR 1 R12C31[1][A] u_test/n815_s1/I2
0.660 0.276 tINS RF 1 R12C31[1][A] u_test/n815_s1/F
0.660 0.000 tNET FF 1 R12C31[1][A] u_test/addr_add_w_21_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R12C31[1][A] u_test/addr_add_w_21_s1/CLK
0.136 0.000 tHld 1 R12C31[1][A] u_test/addr_add_w_21_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path17

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/RD_CYC_CNT_3_s1
To u_test/RD_CYC_CNT_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C33[1][A] u_test/RD_CYC_CNT_3_s1/CLK
0.383 0.247 tC2Q RR 2 R11C33[1][A] u_test/RD_CYC_CNT_3_s1/Q
0.384 0.002 tNET RR 1 R11C33[1][A] u_test/n371_s1/I3
0.660 0.276 tINS RF 1 R11C33[1][A] u_test/n371_s1/F
0.660 0.000 tNET FF 1 R11C33[1][A] u_test/RD_CYC_CNT_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C33[1][A] u_test/RD_CYC_CNT_3_s1/CLK
0.136 0.000 tHld 1 R11C33[1][A] u_test/RD_CYC_CNT_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path18

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/RD_CYC_CNT_14_s1
To u_test/RD_CYC_CNT_14_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C31[1][A] u_test/RD_CYC_CNT_14_s1/CLK
0.383 0.247 tC2Q RR 3 R9C31[1][A] u_test/RD_CYC_CNT_14_s1/Q
0.384 0.002 tNET RR 1 R9C31[1][A] u_test/n360_s1/I3
0.660 0.276 tINS RF 1 R9C31[1][A] u_test/n360_s1/F
0.660 0.000 tNET FF 1 R9C31[1][A] u_test/RD_CYC_CNT_14_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C31[1][A] u_test/RD_CYC_CNT_14_s1/CLK
0.136 0.000 tHld 1 R9C31[1][A] u_test/RD_CYC_CNT_14_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path19

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/RD_CYC_CNT_16_s1
To u_test/RD_CYC_CNT_16_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C31[0][A] u_test/RD_CYC_CNT_16_s1/CLK
0.383 0.247 tC2Q RR 2 R11C31[0][A] u_test/RD_CYC_CNT_16_s1/Q
0.384 0.002 tNET RR 1 R11C31[0][A] u_test/n358_s1/I3
0.660 0.276 tINS RF 1 R11C31[0][A] u_test/n358_s1/F
0.660 0.000 tNET FF 1 R11C31[0][A] u_test/RD_CYC_CNT_16_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R11C31[0][A] u_test/RD_CYC_CNT_16_s1/CLK
0.136 0.000 tHld 1 R11C31[0][A] u_test/RD_CYC_CNT_16_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path20

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/WR_CYC_CNT_3_s1
To u_test/WR_CYC_CNT_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R8C31[0][A] u_test/WR_CYC_CNT_3_s1/CLK
0.383 0.247 tC2Q RR 2 R8C31[0][A] u_test/WR_CYC_CNT_3_s1/Q
0.384 0.002 tNET RR 1 R8C31[0][A] u_test/n233_s1/I3
0.660 0.276 tINS RF 1 R8C31[0][A] u_test/n233_s1/F
0.660 0.000 tNET FF 1 R8C31[0][A] u_test/WR_CYC_CNT_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R8C31[0][A] u_test/WR_CYC_CNT_3_s1/CLK
0.136 0.000 tHld 1 R8C31[0][A] u_test/WR_CYC_CNT_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path21

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/WR_CYC_CNT_12_s1
To u_test/WR_CYC_CNT_12_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C32[1][A] u_test/WR_CYC_CNT_12_s1/CLK
0.383 0.247 tC2Q RR 3 R9C32[1][A] u_test/WR_CYC_CNT_12_s1/Q
0.384 0.002 tNET RR 1 R9C32[1][A] u_test/n224_s1/I3
0.660 0.276 tINS RF 1 R9C32[1][A] u_test/n224_s1/F
0.660 0.000 tNET FF 1 R9C32[1][A] u_test/WR_CYC_CNT_12_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C32[1][A] u_test/WR_CYC_CNT_12_s1/CLK
0.136 0.000 tHld 1 R9C32[1][A] u_test/WR_CYC_CNT_12_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path22

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/WR_CYC_CNT_16_s1
To u_test/WR_CYC_CNT_16_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C33[1][A] u_test/WR_CYC_CNT_16_s1/CLK
0.383 0.247 tC2Q RR 2 R9C33[1][A] u_test/WR_CYC_CNT_16_s1/Q
0.384 0.002 tNET RR 1 R9C33[1][A] u_test/n220_s1/I3
0.660 0.276 tINS RF 1 R9C33[1][A] u_test/n220_s1/F
0.660 0.000 tNET FF 1 R9C33[1][A] u_test/WR_CYC_CNT_16_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R9C33[1][A] u_test/WR_CYC_CNT_16_s1/CLK
0.136 0.000 tHld 1 R9C33[1][A] u_test/WR_CYC_CNT_16_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path23

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/WR_CNT_4_s1
To u_test/WR_CNT_4_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R7C30[0][A] u_test/WR_CNT_4_s1/CLK
0.383 0.247 tC2Q RR 4 R7C30[0][A] u_test/WR_CNT_4_s1/Q
0.384 0.002 tNET RR 1 R7C30[0][A] u_test/n178_s1/I0
0.660 0.276 tINS RF 1 R7C30[0][A] u_test/n178_s1/F
0.660 0.000 tNET FF 1 R7C30[0][A] u_test/WR_CNT_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R7C30[0][A] u_test/WR_CNT_4_s1/CLK
0.136 0.000 tHld 1 R7C30[0][A] u_test/WR_CNT_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path24

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/start_cnt_5_s1
To u_test/start_cnt_5_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R15C33[1][A] u_test/start_cnt_5_s1/CLK
0.383 0.247 tC2Q RR 4 R15C33[1][A] u_test/start_cnt_5_s1/Q
0.384 0.002 tNET RR 1 R15C33[1][A] u_test/n89_s1/I2
0.660 0.276 tINS RF 1 R15C33[1][A] u_test/n89_s1/F
0.660 0.000 tNET FF 1 R15C33[1][A] u_test/start_cnt_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R15C33[1][A] u_test/start_cnt_5_s1/CLK
0.136 0.000 tHld 1 R15C33[1][A] u_test/start_cnt_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path25

Path Summary:

Slack 0.524
Data Arrival Time 0.660
Data Required Time 0.136
From u_test/addr_add_r_15_s0
To u_test/addr_add_r_15_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R14C29[1][A] u_test/addr_add_r_15_s0/CLK
0.383 0.247 tC2Q RR 4 R14C29[1][A] u_test/addr_add_r_15_s0/Q
0.384 0.002 tNET RR 1 R14C29[1][A] u_test/n581_s1/I2
0.660 0.276 tINS RF 1 R14C29[1][A] u_test/n581_s1/F
0.660 0.000 tNET FF 1 R14C29[1][A] u_test/addr_add_r_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 635 BOTTOMSIDE[1] u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136 0.136 tNET RR 1 R14C29[1][A] u_test/addr_add_r_15_s0/CLK
0.136 0.000 tHld 1 R14C29[1][A] u_test/addr_add_r_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_hpram_top/u_hpram_top_0/rd_data_valid_d_Z

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_hpram_top/u_hpram_top_0/rd_data_valid_d_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_hpram_top/u_hpram_top_0/rd_data_valid_d_Z/CLK

MPW2

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_hpram_top/u_hpram_top_0/rd_data_d_Z[23]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_hpram_top/u_hpram_top_0/rd_data_d_Z[23]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_hpram_top/u_hpram_top_0/rd_data_d_Z[23]/CLK

MPW3

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_hpram_top/u_hpram_top_0/rd_data_d_Z[15]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_hpram_top/u_hpram_top_0/rd_data_d_Z[15]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_hpram_top/u_hpram_top_0/rd_data_d_Z[15]/CLK

MPW4

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_hpram_top/u_hpram_top_0/rd_data_d_Z[11]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_hpram_top/u_hpram_top_0/rd_data_d_Z[11]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_hpram_top/u_hpram_top_0/rd_data_d_Z[11]/CLK

MPW5

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_hpram_top/u_hpram_top_0/rd_data_d_Z[30]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_hpram_top/u_hpram_top_0/rd_data_d_Z[30]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_hpram_top/u_hpram_top_0/rd_data_d_Z[30]/CLK

MPW6

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_hpram_top/u_hpram_top_0/rd_data_d_Z[29]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_hpram_top/u_hpram_top_0/rd_data_d_Z[29]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_hpram_top/u_hpram_top_0/rd_data_d_Z[29]/CLK

MPW7

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/d2_Z[2]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/d2_Z[2]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/d2_Z[2]/CLK

MPW8

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/CA_Z[43]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/CA_Z[43]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/CA_Z[43]/CLK

MPW9

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_test/WR_CYC_CNT_14_s1

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_test/WR_CYC_CNT_14_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_test/WR_CYC_CNT_14_s1/CLK

MPW10

MPW Summary:

Slack: 4.019
Actual Width: 4.945
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_test/WR_CYC_CNT_15_s1

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190 0.190 tNET FF u_test/WR_CYC_CNT_15_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136 0.136 tNET RR u_test/WR_CYC_CNT_15_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
635 clk_x1 1.272 0.190
69 curr_state.WRITE_ALL_ADDR 2.079 1.853
59 curr_state.CYC_DONE_WAITE 6.524 1.373
49 WR_CNT[5] 2.475 1.481
48 wr_data_31_9 4.529 1.476
37 check_cnt_scalar 4.288 1.101
36 config_done_Z 5.488 1.376
36 id_reg43_0 4.145 0.774
35 data_mask_d_rst 2.446 3.882
35 n443_4 2.079 2.405

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R9C21 47.22%
R12C13 47.22%
R12C12 45.83%
R13C12 45.83%
R12C22 44.44%
R9C12 44.44%
R12C29 41.67%
R12C30 41.67%
R8C7 40.28%
R11C30 40.28%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk_x1 -period 10 -waveform {0 5} [get_nets {clk_x1}]
TC_CLOCK Actived create_clock -name clk_x2 -period 5 -waveform {0 2.5} [get_nets {memory_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {clk_x1 clk_x2}]