SinProject Project Status (07/28/2019 - 14:33:06)
Project File: SinusCosinusFunction01.xise Parser Errors: No Errors
Module Name: SinProject Implementation State: Placed and Routed
Target Device: xc6slx9-3csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
4 Warnings (3 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 69 11,440 1%  
    Number used as Flip Flops 69      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 32 5,720 1%  
    Number used as logic 28 5,720 1%  
        Number using O6 output only 20      
        Number using O5 output only 0      
        Number using O5 and O6 8      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 4      
        Number with same-slice register load 4      
        Number with same-slice carry load 0      
        Number with other load 0      
Number of occupied Slices 19 1,430 1%  
Number of MUXCYs used 8 2,860 1%  
Number of LUT Flip Flop pairs used 65      
    Number with an unused Flip Flop 1 65 1%  
    Number with an unused LUT 33 65 50%  
    Number of fully used LUT-FF pairs 31 65 47%  
    Number of unique control sets 5      
    Number of slice register sites lost
        to control set restrictions
11 11,440 1%  
Number of bonded IOBs 45 200 22%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 1 64 1%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.01      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentniedz. 28. lip 14:32:32 201903 Warnings (3 new)3 Infos (3 new)
Translation ReportCurrentniedz. 28. lip 14:32:38 2019000
Map ReportCurrentniedz. 28. lip 14:32:50 201901 Warning (0 new)6 Infos (0 new)
Place and Route ReportCurrentniedz. 28. lip 14:32:57 2019003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentniedz. 28. lip 14:33:04 2019004 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 07/28/2019 - 14:33:06