FlyingDutch Napisano Grudzień 1, 2018 Udostępnij Napisano Grudzień 1, 2018 (edytowany) Cześć, ostatnio dość dużo się mówi (także na Forbot.pl) o nowej otwartej architekturze RISC-V. Pojawia się coraz więcej różnych zestawów uruchomieniowych z tą architekturą. Oto kolejny przykład: Lichee Tang : https://www.banggood.com/Lichee-Tang-64Mbit-SDRAM-Onboard-FPGA-Downloader-Dual-Flash-RISC-V-Development-Board-p-1352386.html?rmmds=myorder&cur_warehouse=CN Właściwie to nie byłem zdecydowany w jakim dziale umieścić ten post, ale stwierdziłem, że najbardziej pasuje do tego działu. Skąd ta trudność w klasyfikacji: otóż jest to dość duży układ FPGA około 20 K logic units. Oparty na chipie FPGA - EG4S20 firmy Anlogic. Na tym układzie FPGA jest zaimplementowany jako soft-Core (podobnie jak opisywane Picoblaze, Microblaze, czy NIOSII) dwurdzieniowy CPU o architekturze RISC-V. Tutaj kilka linków dot. tej płytki: https://www.cnx-software.com/2018/09/04/licheetang-anlogic-eg4s20-fpga-board-targets-risc-v-development/ https://www.cnx-software.com/tag/anlogic/ https://www.elektroda.pl/rtvforum/topic3496915.html Zamówiłem tą płytkę, jak dotrze (pewnie około miesiąca) i będę miał chwilę wolnego czasu to podzielę się wrażeniami z uruchomienia. jedyne czego się obawiam to brak porządnej dokumentacji. Pozdrawiam BTW: zamieszczam jeszcze linki do dokładniejszego opisu i środowiska (IDE) do programowania układu: http://myosuploads3.banggood.com/products/20181113/20181113213840SipeedlicheeTangSpecificationsV1.0.pdf https://github.com/Lichee-Pi/Tang_E203_Mini Jeśli ktoś ma więcej informacji o tym zestawie to niech się podzieli nimi - z chęcią się zapoznam 🙂 Edytowano Grudzień 1, 2018 przez FlyingDutch 1 Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 6, 2018 Autor tematu Udostępnij Grudzień 6, 2018 (edytowany) Cześć, tutaj ostatni update ze świata "RISC-V" (tym razem quad core + FPGA) ze znanej firmy (Microchip/Microsemi); https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpgahttps://www.sifive.com/press/industrys-first-risc-v-soc-fpga-architecture-brings Pozdrawiam Edytowano Grudzień 6, 2018 przez FlyingDutch 1 Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 8, 2018 Autor tematu Udostępnij Grudzień 8, 2018 (edytowany) Cześć, na youtube.com ukazał się dwunastoczęściowy tutorial dotyczący programowania "RISC-V" w jego assemblerze: https://www.youtube.com/watch?v=eR50d6CDOys A tutaj jeszcze jeden ciekawy artykuł dotyczący zastosowań tej nowej architektury: https://www.eetimes.com/document.asp?doc_id=1334032 Pozdrawiam Edytowano Grudzień 8, 2018 przez FlyingDutch 2 Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 10, 2018 Autor tematu Udostępnij Grudzień 10, 2018 Cześć, gdyby ktoś chciał "wypróbować" architekturę RISC_V (a właściwie listę rozkazów bo to definiuje RISC-V w podstawowej wersji) to można to zrobić na układzie FPGA (i to wcale nie jakimś dużym ). Tutaj spis darmowych IP-Cores z tą architekturą: https://github.com/riscv/riscv-wiki/wiki/RISC-V-Cores-and-SoCs A te dwa projekty polecono mi jako szczególnie ciekawe na początek: https://discourse.tinyfpga.com/t/riscv-example-project-on-tinyfpga-bx/451 https://github.com/SpinalHDL/VexRiscv#area-usage-and-maximal-frequency Pozdrawiam 1 Cytuj Link do komentarza Share on other sites More sharing options...
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Treker (Damian Szymański) Grudzień 11, 2018 Udostępnij Grudzień 11, 2018 @FlyingDutch, widzę, że "wkręciłeś" się mocno w ten temat 😉 Masz za sobą już jakieś eksperymenty praktyczne? Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 12, 2018 Autor tematu Udostępnij Grudzień 12, 2018 15 godzin temu, Treker napisał: @FlyingDutch, widzę, że "wkręciłeś" się mocno w ten temat 😉 Masz za sobą już jakieś eksperymenty praktyczne? Cześć, niestety nie - do końca roku mam takie obciążenie w pracy (z projektem), że nie ma szans nawet na kilka godzin wolnego czasu. Tylko śledzę temat na kilku forach o elektronice. Tutaj ostatnio była ciekawa dyskusja: http://www.eevblog.com/forum/microcontrollers/risc-v-assembly-language-programming-tutorial-on-youtube/ Jak będę miał chwilę wolnego czasu to chciałbym zapoznać się z tą architekturą "RISC-V" na płytce FPGA jako IP-Core (darmowy). Pozdrawiam 1 Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 22, 2018 Autor tematu Udostępnij Grudzień 22, 2018 Cześć, mam kilka dni wolnego i spróbuję uruchomić "RISC-V" jako IP-Core na płytce FPGA - jak coś z tego wyjdzie to opiszę na forum. Pozdrawiam 1 Cytuj Link do komentarza Share on other sites More sharing options...
Treker (Damian Szymański) Grudzień 22, 2018 Udostępnij Grudzień 22, 2018 Planujesz zrobić coś konkretnego, czy na razie jakieś "Hello world"? Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 22, 2018 Autor tematu Udostępnij Grudzień 22, 2018 58 minut temu, Treker napisał: Planujesz zrobić coś konkretnego, czy na razie jakieś "Hello world"? Cześć, próbuję wygenerować IP-Core z zadanymi parametrami dla VexRiscv (taka pośrednia wersja - nie najbiedniejsza i nie najbogatsza) i zbudować "RISC_V gcc" (kompilator), ale już w tej fazie napotkałem pewne trudności (na poziomie distro Linux'a pod którym to robię). Pewnie zajmie mi kilka dni zanim uda mi się wszystko uruchomić. Dam znać jak skończę. Pozdrawiam. Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 25, 2018 Autor tematu Udostępnij Grudzień 25, 2018 (edytowany) Cześć, po instalacji wszystkich wymaganych zależności i pakietów: 1) Java 8 2) Scala 2.11.x 3) Scala SBT 4) SpinalHDL 4) Verilator Patrz: #Dependencies w tym linku: https://github.com/SpinalHDL/VexRiscv#area-usage-and-maximal-frequency udało mi się wygenerować VexRiscv w minimalnej konfiguracji (powinien zmieścić się na płytce FPGA Mimas V.2 Firmy Numato ze Spartanem 6): https://numato.com/product/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram a być może zmieści się na płytce z kursu FPGA : Elbert V. Co ciekawe po generacji konfiguracji (projektu w języku Scala) powstał tylko jeden plik wynikowy w Verilogu (HDL) o nazwie: VexRiscv.v w którym zawiera się cały projekt CPU. Tutaj jego zawartość: // Generator : SpinalHDL v1.2.2 git head : 3159d9865a8de00378e0b0405c338a97c2f5a601 // Date : 25/12/2018, 13:52:16 // Component : VexRiscv `define Src2CtrlEnum_defaultEncoding_type [1:0] `define Src2CtrlEnum_defaultEncoding_RS 2'b00 `define Src2CtrlEnum_defaultEncoding_IMI 2'b01 `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 `define AluCtrlEnum_defaultEncoding_type [1:0] `define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 `define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 `define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 `define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 `define EnvCtrlEnum_defaultEncoding_type [0:0] `define EnvCtrlEnum_defaultEncoding_NONE 1'b0 `define EnvCtrlEnum_defaultEncoding_XRET 1'b1 `define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] `define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 `define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 `define AluBitwiseCtrlEnum_defaultEncoding_SRC1 2'b11 `define BranchCtrlEnum_defaultEncoding_type [1:0] `define BranchCtrlEnum_defaultEncoding_INC 2'b00 `define BranchCtrlEnum_defaultEncoding_B 2'b01 `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 `define Src1CtrlEnum_defaultEncoding_type [1:0] `define Src1CtrlEnum_defaultEncoding_RS 2'b00 `define Src1CtrlEnum_defaultEncoding_IMU 2'b01 `define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 module StreamFifoLowLatency ( input io_push_valid, output io_push_ready, input io_push_payload_error, input [31:0] io_push_payload_inst, output reg io_pop_valid, input io_pop_ready, output reg io_pop_payload_error, output reg [31:0] io_pop_payload_inst, input io_flush, output [0:0] io_occupancy, input clk, input reset); wire [0:0] _zz_5_; reg _zz_1_; reg pushPtr_willIncrement; reg pushPtr_willClear; wire pushPtr_willOverflowIfInc; wire pushPtr_willOverflow; reg popPtr_willIncrement; reg popPtr_willClear; wire popPtr_willOverflowIfInc; wire popPtr_willOverflow; wire ptrMatch; reg risingOccupancy; wire empty; wire full; wire pushing; wire popping; wire [32:0] _zz_2_; wire [32:0] _zz_3_; reg [32:0] _zz_4_; assign _zz_5_ = _zz_2_[0 : 0]; always @ (*) begin _zz_1_ = 1'b0; pushPtr_willIncrement = 1'b0; if(pushing)begin _zz_1_ = 1'b1; pushPtr_willIncrement = 1'b1; end end always @ (*) begin pushPtr_willClear = 1'b0; popPtr_willClear = 1'b0; if(io_flush)begin pushPtr_willClear = 1'b1; popPtr_willClear = 1'b1; end end assign pushPtr_willOverflowIfInc = 1'b1; assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); always @ (*) begin popPtr_willIncrement = 1'b0; if(popping)begin popPtr_willIncrement = 1'b1; end end assign popPtr_willOverflowIfInc = 1'b1; assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); assign ptrMatch = 1'b1; assign empty = (ptrMatch && (! risingOccupancy)); assign full = (ptrMatch && risingOccupancy); assign pushing = (io_push_valid && io_push_ready); assign popping = (io_pop_valid && io_pop_ready); assign io_push_ready = (! full); always @ (*) begin if((! empty))begin io_pop_valid = 1'b1; io_pop_payload_error = _zz_5_[0]; io_pop_payload_inst = _zz_2_[32 : 1]; end else begin io_pop_valid = io_push_valid; io_pop_payload_error = io_push_payload_error; io_pop_payload_inst = io_push_payload_inst; end end assign _zz_2_ = _zz_3_; assign io_occupancy = (risingOccupancy && ptrMatch); assign _zz_3_ = _zz_4_; always @ (posedge clk or posedge reset) begin if (reset) begin risingOccupancy <= 1'b0; end else begin if((pushing != popping))begin risingOccupancy <= pushing; end if(io_flush)begin risingOccupancy <= 1'b0; end end end always @ (posedge clk) begin if(_zz_1_)begin _zz_4_ <= {io_push_payload_inst,io_push_payload_error}; end end endmodule module VexRiscv ( output iBus_cmd_valid, input iBus_cmd_ready, output [31:0] iBus_cmd_payload_pc, input iBus_rsp_valid, input iBus_rsp_payload_error, input [31:0] iBus_rsp_payload_inst, input timerInterrupt, input externalInterrupt, output dBus_cmd_valid, input dBus_cmd_ready, output dBus_cmd_payload_wr, output [31:0] dBus_cmd_payload_address, output [31:0] dBus_cmd_payload_data, output [1:0] dBus_cmd_payload_size, input dBus_rsp_ready, input dBus_rsp_error, input [31:0] dBus_rsp_data, input clk, input reset); wire _zz_138_; wire _zz_139_; reg [31:0] _zz_140_; reg [31:0] _zz_141_; wire _zz_142_; wire _zz_143_; wire _zz_144_; wire [31:0] _zz_145_; wire [0:0] _zz_146_; wire _zz_147_; wire _zz_148_; wire _zz_149_; wire _zz_150_; wire _zz_151_; wire [1:0] _zz_152_; wire [1:0] _zz_153_; wire _zz_154_; wire [1:0] _zz_155_; wire [1:0] _zz_156_; wire [2:0] _zz_157_; wire [31:0] _zz_158_; wire [2:0] _zz_159_; wire [0:0] _zz_160_; wire [2:0] _zz_161_; wire [0:0] _zz_162_; wire [2:0] _zz_163_; wire [0:0] _zz_164_; wire [2:0] _zz_165_; wire [0:0] _zz_166_; wire [2:0] _zz_167_; wire [0:0] _zz_168_; wire [0:0] _zz_169_; wire [0:0] _zz_170_; wire [0:0] _zz_171_; wire [0:0] _zz_172_; wire [0:0] _zz_173_; wire [0:0] _zz_174_; wire [0:0] _zz_175_; wire [0:0] _zz_176_; wire [0:0] _zz_177_; wire [2:0] _zz_178_; wire [4:0] _zz_179_; wire [11:0] _zz_180_; wire [11:0] _zz_181_; wire [31:0] _zz_182_; wire [31:0] _zz_183_; wire [31:0] _zz_184_; wire [31:0] _zz_185_; wire [1:0] _zz_186_; wire [31:0] _zz_187_; wire [1:0] _zz_188_; wire [1:0] _zz_189_; wire [31:0] _zz_190_; wire [32:0] _zz_191_; wire [19:0] _zz_192_; wire [11:0] _zz_193_; wire [11:0] _zz_194_; wire [0:0] _zz_195_; wire [0:0] _zz_196_; wire [0:0] _zz_197_; wire [0:0] _zz_198_; wire [0:0] _zz_199_; wire [0:0] _zz_200_; wire _zz_201_; wire _zz_202_; wire _zz_203_; wire [0:0] _zz_204_; wire [0:0] _zz_205_; wire [2:0] _zz_206_; wire [2:0] _zz_207_; wire _zz_208_; wire [0:0] _zz_209_; wire [16:0] _zz_210_; wire [31:0] _zz_211_; wire _zz_212_; wire _zz_213_; wire _zz_214_; wire _zz_215_; wire [0:0] _zz_216_; wire [0:0] _zz_217_; wire [4:0] _zz_218_; wire [4:0] _zz_219_; wire _zz_220_; wire [0:0] _zz_221_; wire [13:0] _zz_222_; wire [31:0] _zz_223_; wire [31:0] _zz_224_; wire [31:0] _zz_225_; wire [31:0] _zz_226_; wire [31:0] _zz_227_; wire [31:0] _zz_228_; wire [31:0] _zz_229_; wire [31:0] _zz_230_; wire [0:0] _zz_231_; wire [2:0] _zz_232_; wire _zz_233_; wire [2:0] _zz_234_; wire [2:0] _zz_235_; wire _zz_236_; wire [0:0] _zz_237_; wire [11:0] _zz_238_; wire [31:0] _zz_239_; wire [31:0] _zz_240_; wire _zz_241_; wire [31:0] _zz_242_; wire [31:0] _zz_243_; wire _zz_244_; wire _zz_245_; wire [0:0] _zz_246_; wire [0:0] _zz_247_; wire _zz_248_; wire [0:0] _zz_249_; wire [8:0] _zz_250_; wire [31:0] _zz_251_; wire [31:0] _zz_252_; wire [31:0] _zz_253_; wire [0:0] _zz_254_; wire [0:0] _zz_255_; wire [2:0] _zz_256_; wire [2:0] _zz_257_; wire _zz_258_; wire [0:0] _zz_259_; wire [5:0] _zz_260_; wire [31:0] _zz_261_; wire [31:0] _zz_262_; wire [31:0] _zz_263_; wire [31:0] _zz_264_; wire _zz_265_; wire _zz_266_; wire _zz_267_; wire [1:0] _zz_268_; wire [1:0] _zz_269_; wire _zz_270_; wire [0:0] _zz_271_; wire [2:0] _zz_272_; wire [31:0] _zz_273_; wire [31:0] _zz_274_; wire [31:0] _zz_275_; wire [31:0] _zz_276_; wire _zz_277_; wire [0:0] _zz_278_; wire [0:0] _zz_279_; wire [3:0] _zz_280_; wire [3:0] _zz_281_; wire _zz_282_; wire _zz_283_; wire [31:0] _zz_284_; wire [31:0] _zz_285_; wire [31:0] _zz_286_; wire _zz_287_; wire [31:0] _zz_288_; wire [31:0] _zz_289_; wire [31:0] _zz_290_; wire [31:0] _zz_291_; wire [31:0] _zz_292_; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_1_; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_2_; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_3_; wire decode_CSR_WRITE_OPCODE; wire decode_SRC_USE_SUB_LESS; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_8_; wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; wire [31:0] decode_SRC2; wire [31:0] memory_PC; wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; wire `ShiftCtrlEnum_defaultEncoding_type _zz_11_; wire `ShiftCtrlEnum_defaultEncoding_type _zz_12_; wire `ShiftCtrlEnum_defaultEncoding_type _zz_13_; wire [31:0] execute_BRANCH_CALC; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] decode_SRC1; wire execute_BRANCH_DO; wire decode_CSR_READ_OPCODE; wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; wire `BranchCtrlEnum_defaultEncoding_type _zz_15_; wire `BranchCtrlEnum_defaultEncoding_type _zz_16_; wire [31:0] decode_RS1; wire decode_IS_CSR; wire [1:0] memory_MEMORY_ADDRESS_LOW; wire [1:0] execute_MEMORY_ADDRESS_LOW; wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; wire `AluCtrlEnum_defaultEncoding_type _zz_17_; wire `AluCtrlEnum_defaultEncoding_type _zz_18_; wire `AluCtrlEnum_defaultEncoding_type _zz_19_; wire decode_BYPASSABLE_EXECUTE_STAGE; wire decode_MEMORY_ENABLE; wire decode_SRC_LESS_UNSIGNED; wire [31:0] decode_RS2; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] _zz_20_; wire [31:0] execute_PC; wire [31:0] execute_RS1; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; wire `BranchCtrlEnum_defaultEncoding_type _zz_21_; wire _zz_22_; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; wire [31:0] memory_REGFILE_WRITE_DATA; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; wire _zz_24_; wire [31:0] _zz_25_; wire [31:0] _zz_26_; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC_USE_SUB_LESS; wire [31:0] _zz_27_; wire [31:0] _zz_28_; wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; wire `Src2CtrlEnum_defaultEncoding_type _zz_29_; wire [31:0] _zz_30_; wire [31:0] _zz_31_; wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; wire `Src1CtrlEnum_defaultEncoding_type _zz_32_; wire [31:0] _zz_33_; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; wire `AluCtrlEnum_defaultEncoding_type _zz_34_; wire [31:0] _zz_35_; wire [31:0] execute_SRC2; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_36_; wire [31:0] _zz_37_; wire _zz_38_; reg _zz_39_; wire [31:0] _zz_40_; wire [31:0] _zz_41_; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire `Src1CtrlEnum_defaultEncoding_type _zz_42_; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43_; wire _zz_44_; wire _zz_45_; wire _zz_46_; wire `AluCtrlEnum_defaultEncoding_type _zz_47_; wire `BranchCtrlEnum_defaultEncoding_type _zz_48_; wire `EnvCtrlEnum_defaultEncoding_type _zz_49_; wire _zz_50_; wire _zz_51_; wire _zz_52_; wire `ShiftCtrlEnum_defaultEncoding_type _zz_53_; wire `Src2CtrlEnum_defaultEncoding_type _zz_54_; wire _zz_55_; wire _zz_56_; wire _zz_57_; reg [31:0] _zz_58_; wire [31:0] execute_SRC1; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_59_; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_60_; wire _zz_61_; wire _zz_62_; wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_63_; reg [31:0] _zz_64_; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; wire [31:0] memory_INSTRUCTION; wire memory_MEMORY_ENABLE; wire [31:0] _zz_65_; wire [1:0] _zz_66_; wire [31:0] execute_RS2; wire [31:0] execute_SRC_ADD; wire [31:0] execute_INSTRUCTION; wire execute_ALIGNEMENT_FAULT; wire execute_MEMORY_ENABLE; reg [31:0] _zz_67_; wire [31:0] _zz_68_; wire [31:0] _zz_69_; wire [31:0] _zz_70_; wire [31:0] _zz_71_; wire [31:0] writeBack_PC /* verilator public */ ; wire [31:0] writeBack_INSTRUCTION /* verilator public */ ; wire [31:0] decode_PC /* verilator public */ ; wire [31:0] decode_INSTRUCTION /* verilator public */ ; wire decode_arbitration_haltItself /* verilator public */ ; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; wire decode_arbitration_flushAll /* verilator public */ ; wire decode_arbitration_redoIt; wire decode_arbitration_isValid /* verilator public */ ; wire decode_arbitration_isStuck; wire decode_arbitration_isStuckByOthers; wire decode_arbitration_isFlushed; wire decode_arbitration_isMoving; wire decode_arbitration_isFiring; reg execute_arbitration_haltItself; wire execute_arbitration_haltByOther; reg execute_arbitration_removeIt; reg execute_arbitration_flushAll; wire execute_arbitration_redoIt; reg execute_arbitration_isValid; wire execute_arbitration_isStuck; wire execute_arbitration_isStuckByOthers; wire execute_arbitration_isFlushed; wire execute_arbitration_isMoving; wire execute_arbitration_isFiring; reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; reg memory_arbitration_flushAll; wire memory_arbitration_redoIt; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; wire memory_arbitration_isFlushed; wire memory_arbitration_isMoving; wire memory_arbitration_isFiring; wire writeBack_arbitration_haltItself; wire writeBack_arbitration_haltByOther; reg writeBack_arbitration_removeIt; wire writeBack_arbitration_flushAll; wire writeBack_arbitration_redoIt; reg writeBack_arbitration_isValid /* verilator public */ ; wire writeBack_arbitration_isStuck; wire writeBack_arbitration_isStuckByOthers; wire writeBack_arbitration_isFlushed; wire writeBack_arbitration_isMoving; wire writeBack_arbitration_isFiring /* verilator public */ ; wire _zz_72_; reg _zz_73_; reg [31:0] _zz_74_; wire contextSwitching; reg [1:0] CsrPlugin_privilege; wire _zz_75_; wire [31:0] _zz_76_; wire IBusSimplePlugin_jump_pcLoad_valid; wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; wire [1:0] _zz_77_; wire IBusSimplePlugin_fetchPc_preOutput_valid; wire IBusSimplePlugin_fetchPc_preOutput_ready; wire [31:0] IBusSimplePlugin_fetchPc_preOutput_payload; wire _zz_78_; wire IBusSimplePlugin_fetchPc_output_valid; wire IBusSimplePlugin_fetchPc_output_ready; wire [31:0] IBusSimplePlugin_fetchPc_output_payload; reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; reg IBusSimplePlugin_fetchPc_inc; reg IBusSimplePlugin_fetchPc_propagatePc; reg [31:0] IBusSimplePlugin_fetchPc_pc; reg IBusSimplePlugin_fetchPc_samplePcNext; reg _zz_79_; wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; reg IBusSimplePlugin_iBusRsp_stages_0_halt; wire IBusSimplePlugin_iBusRsp_stages_0_inputSample; wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; wire IBusSimplePlugin_iBusRsp_stages_1_halt; wire IBusSimplePlugin_iBusRsp_stages_1_inputSample; wire _zz_80_; wire _zz_81_; wire _zz_82_; wire _zz_83_; reg _zz_84_; reg IBusSimplePlugin_iBusRsp_readyForError; wire IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; wire IBusSimplePlugin_iBusRsp_inputBeforeStage_ready; wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_raw; wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; wire IBusSimplePlugin_injector_decodeInput_valid; wire IBusSimplePlugin_injector_decodeInput_ready; wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; reg _zz_85_; reg [31:0] _zz_86_; reg _zz_87_; reg [31:0] _zz_88_; reg _zz_89_; reg IBusSimplePlugin_injector_nextPcCalc_valids_0; reg IBusSimplePlugin_injector_nextPcCalc_0; reg IBusSimplePlugin_injector_nextPcCalc_1; reg IBusSimplePlugin_injector_nextPcCalc_2; reg IBusSimplePlugin_injector_nextPcCalc_3; reg IBusSimplePlugin_injector_decodeRemoved; reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; wire IBusSimplePlugin_cmd_valid; wire IBusSimplePlugin_cmd_ready; wire [31:0] IBusSimplePlugin_cmd_payload_pc; reg [2:0] IBusSimplePlugin_pendingCmd; wire [2:0] IBusSimplePlugin_pendingCmdNext; reg [2:0] IBusSimplePlugin_rspJoin_discardCounter; wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid; wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready; wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; wire IBusSimplePlugin_rspJoin_issueDetected; wire IBusSimplePlugin_rspJoin_join_valid; wire IBusSimplePlugin_rspJoin_join_ready; wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; wire IBusSimplePlugin_rspJoin_join_payload_isRvc; wire _zz_90_; wire execute_DBusSimplePlugin_cmdSent; reg [31:0] _zz_91_; reg [3:0] _zz_92_; wire [3:0] execute_DBusSimplePlugin_formalMask; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; wire _zz_93_; reg [31:0] _zz_94_; wire _zz_95_; reg [31:0] _zz_96_; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; wire [1:0] CsrPlugin_mtvec_mode; wire [29:0] CsrPlugin_mtvec_base; reg [31:0] CsrPlugin_mepc; reg CsrPlugin_mstatus_MIE; reg CsrPlugin_mstatus_MPIE; reg [1:0] CsrPlugin_mstatus_MPP; reg CsrPlugin_mip_MEIP; reg CsrPlugin_mip_MTIP; reg CsrPlugin_mip_MSIP; reg CsrPlugin_mie_MEIE; reg CsrPlugin_mie_MTIE; reg CsrPlugin_mie_MSIE; reg CsrPlugin_mcause_interrupt; reg [3:0] CsrPlugin_mcause_exceptionCode; reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; wire [31:0] CsrPlugin_medeleg; wire [31:0] CsrPlugin_mideleg; wire _zz_97_; wire _zz_98_; wire _zz_99_; reg CsrPlugin_interrupt; reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; reg [1:0] CsrPlugin_interruptTargetPrivilege; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_done; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException; wire [1:0] CsrPlugin_targetPrivilege; wire [3:0] CsrPlugin_trapCause; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; reg [31:0] execute_CsrPlugin_readData; wire execute_CsrPlugin_writeInstruction; wire execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; wire [22:0] _zz_100_; wire _zz_101_; wire _zz_102_; wire _zz_103_; wire _zz_104_; wire _zz_105_; wire _zz_106_; wire `Src2CtrlEnum_defaultEncoding_type _zz_107_; wire `ShiftCtrlEnum_defaultEncoding_type _zz_108_; wire `EnvCtrlEnum_defaultEncoding_type _zz_109_; wire `BranchCtrlEnum_defaultEncoding_type _zz_110_; wire `AluCtrlEnum_defaultEncoding_type _zz_111_; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_112_; wire `Src1CtrlEnum_defaultEncoding_type _zz_113_; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; wire [31:0] decode_RegFilePlugin_rs2Data; reg writeBack_RegFilePlugin_regFileWrite_valid /* verilator public */ ; wire [4:0] writeBack_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; wire [31:0] writeBack_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; reg _zz_114_; reg [31:0] execute_IntAluPlugin_bitwise; reg [31:0] _zz_115_; reg [31:0] _zz_116_; wire _zz_117_; reg [19:0] _zz_118_; wire _zz_119_; reg [19:0] _zz_120_; reg [31:0] _zz_121_; wire [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; wire execute_LightShifterPlugin_isShift; reg [4:0] execute_LightShifterPlugin_amplitudeReg; wire [4:0] execute_LightShifterPlugin_amplitude; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; reg [31:0] _zz_122_; reg _zz_123_; reg _zz_124_; wire _zz_125_; reg _zz_126_; reg [4:0] _zz_127_; wire execute_BranchPlugin_eq; wire [2:0] _zz_128_; reg _zz_129_; reg _zz_130_; wire [31:0] execute_BranchPlugin_branch_src1; wire _zz_131_; reg [10:0] _zz_132_; wire _zz_133_; reg [19:0] _zz_134_; wire _zz_135_; reg [18:0] _zz_136_; reg [31:0] _zz_137_; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; reg [31:0] decode_to_execute_RS2; reg decode_to_execute_SRC_LESS_UNSIGNED; reg decode_to_execute_MEMORY_ENABLE; reg execute_to_memory_MEMORY_ENABLE; reg memory_to_writeBack_MEMORY_ENABLE; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; reg decode_to_execute_IS_CSR; reg [31:0] decode_to_execute_RS1; reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; reg decode_to_execute_CSR_READ_OPCODE; reg execute_to_memory_BRANCH_DO; reg [31:0] decode_to_execute_SRC1; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; reg [31:0] execute_to_memory_BRANCH_CALC; reg [31:0] decode_to_execute_INSTRUCTION; reg [31:0] execute_to_memory_INSTRUCTION; reg [31:0] memory_to_writeBack_INSTRUCTION; reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; reg [31:0] decode_to_execute_SRC2; reg decode_to_execute_REGFILE_WRITE_VALID; reg execute_to_memory_REGFILE_WRITE_VALID; reg memory_to_writeBack_REGFILE_WRITE_VALID; reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; reg decode_to_execute_SRC_USE_SUB_LESS; reg decode_to_execute_CSR_WRITE_OPCODE; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; assign _zz_147_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); assign _zz_148_ = (! execute_arbitration_isStuckByOthers); assign _zz_149_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); assign _zz_150_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); assign _zz_151_ = (IBusSimplePlugin_fetchPc_preOutput_valid && IBusSimplePlugin_fetchPc_preOutput_ready); assign _zz_152_ = writeBack_INSTRUCTION[13 : 12]; assign _zz_153_ = writeBack_INSTRUCTION[29 : 28]; assign _zz_154_ = execute_INSTRUCTION[13]; assign _zz_155_ = (_zz_77_ & (~ _zz_156_)); assign _zz_156_ = (_zz_77_ - (2'b01)); assign _zz_157_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)}; assign _zz_158_ = {29'd0, _zz_157_}; assign _zz_159_ = (IBusSimplePlugin_pendingCmd + _zz_161_); assign _zz_160_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); assign _zz_161_ = {2'd0, _zz_160_}; assign _zz_162_ = iBus_rsp_valid; assign _zz_163_ = {2'd0, _zz_162_}; assign _zz_164_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000))); assign _zz_165_ = {2'd0, _zz_164_}; assign _zz_166_ = iBus_rsp_valid; assign _zz_167_ = {2'd0, _zz_166_}; assign _zz_168_ = _zz_100_[0 : 0]; assign _zz_169_ = _zz_100_[1 : 1]; assign _zz_170_ = _zz_100_[2 : 2]; assign _zz_171_ = _zz_100_[7 : 7]; assign _zz_172_ = _zz_100_[8 : 8]; assign _zz_173_ = _zz_100_[9 : 9]; assign _zz_174_ = _zz_100_[15 : 15]; assign _zz_175_ = _zz_100_[16 : 16]; assign _zz_176_ = _zz_100_[18 : 18]; assign _zz_177_ = execute_SRC_LESS; assign _zz_178_ = (3'b100); assign _zz_179_ = decode_INSTRUCTION[19 : 15]; assign _zz_180_ = decode_INSTRUCTION[31 : 20]; assign _zz_181_ = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; assign _zz_182_ = ($signed(_zz_183_) + $signed(_zz_187_)); assign _zz_183_ = ($signed(_zz_184_) + $signed(_zz_185_)); assign _zz_184_ = execute_SRC1; assign _zz_185_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); assign _zz_186_ = (execute_SRC_USE_SUB_LESS ? _zz_188_ : _zz_189_); assign _zz_187_ = {{30{_zz_186_[1]}}, _zz_186_}; assign _zz_188_ = (2'b01); assign _zz_189_ = (2'b00); assign _zz_190_ = (_zz_191_ >>> 1); assign _zz_191_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; assign _zz_192_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; assign _zz_193_ = execute_INSTRUCTION[31 : 20]; assign _zz_194_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; assign _zz_195_ = execute_CsrPlugin_writeData[7 : 7]; assign _zz_196_ = execute_CsrPlugin_writeData[3 : 3]; assign _zz_197_ = execute_CsrPlugin_writeData[3 : 3]; assign _zz_198_ = execute_CsrPlugin_writeData[11 : 11]; assign _zz_199_ = execute_CsrPlugin_writeData[7 : 7]; assign _zz_200_ = execute_CsrPlugin_writeData[3 : 3]; assign _zz_201_ = 1'b1; assign _zz_202_ = 1'b1; assign _zz_203_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); assign _zz_204_ = ((decode_INSTRUCTION & _zz_211_) == (32'b00000000000000000001000000000000)); assign _zz_205_ = _zz_103_; assign _zz_206_ = {_zz_103_,{_zz_212_,_zz_213_}}; assign _zz_207_ = (3'b000); assign _zz_208_ = ({_zz_214_,_zz_215_} != (2'b00)); assign _zz_209_ = ({_zz_216_,_zz_217_} != (2'b00)); assign _zz_210_ = {(_zz_218_ != _zz_219_),{_zz_220_,{_zz_221_,_zz_222_}}}; assign _zz_211_ = (32'b00000000000000000001000000000000); assign _zz_212_ = ((decode_INSTRUCTION & _zz_223_) == (32'b00000000000000000001000000000000)); assign _zz_213_ = ((decode_INSTRUCTION & _zz_224_) == (32'b00000000000000000010000000000000)); assign _zz_214_ = ((decode_INSTRUCTION & _zz_225_) == (32'b00000000000000000010000000000000)); assign _zz_215_ = ((decode_INSTRUCTION & _zz_226_) == (32'b00000000000000000001000000000000)); assign _zz_216_ = (_zz_227_ == _zz_228_); assign _zz_217_ = (_zz_229_ == _zz_230_); assign _zz_218_ = {_zz_103_,{_zz_231_,_zz_232_}}; assign _zz_219_ = (5'b00000); assign _zz_220_ = (_zz_233_ != (1'b0)); assign _zz_221_ = (_zz_234_ != _zz_235_); assign _zz_222_ = {_zz_236_,{_zz_237_,_zz_238_}}; assign _zz_223_ = (32'b00000000000000000011000000000000); assign _zz_224_ = (32'b00000000000000000011000000000000); assign _zz_225_ = (32'b00000000000000000010000000010000); assign _zz_226_ = (32'b00000000000000000101000000000000); assign _zz_227_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000)); assign _zz_228_ = (32'b00000000000000000000000001000000); assign _zz_229_ = (decode_INSTRUCTION & (32'b00000000000000000011000001000000)); assign _zz_230_ = (32'b00000000000000000000000001000000); assign _zz_231_ = _zz_102_; assign _zz_232_ = {(_zz_239_ == _zz_240_),{_zz_241_,_zz_104_}}; assign _zz_233_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); assign _zz_234_ = {(_zz_242_ == _zz_243_),{_zz_244_,_zz_245_}}; assign _zz_235_ = (3'b000); assign _zz_236_ = (_zz_101_ != (1'b0)); assign _zz_237_ = (_zz_105_ != (1'b0)); assign _zz_238_ = {(_zz_246_ != _zz_247_),{_zz_248_,{_zz_249_,_zz_250_}}}; assign _zz_239_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); assign _zz_240_ = (32'b00000000000000000001000000010000); assign _zz_241_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); assign _zz_242_ = (decode_INSTRUCTION & (32'b00000000000000000100000000000100)); assign _zz_243_ = (32'b00000000000000000100000000000000); assign _zz_244_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); assign _zz_245_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000100)) == (32'b00000000000000000001000000000000)); assign _zz_246_ = ((decode_INSTRUCTION & _zz_251_) == (32'b00000000000000000000000001000000)); assign _zz_247_ = (1'b0); assign _zz_248_ = ((_zz_252_ == _zz_253_) != (1'b0)); assign _zz_249_ = ({_zz_254_,_zz_255_} != (2'b00)); assign _zz_250_ = {(_zz_256_ != _zz_257_),{_zz_258_,{_zz_259_,_zz_260_}}}; assign _zz_251_ = (32'b00000000000000000000000001011000); assign _zz_252_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010000)); assign _zz_253_ = (32'b00000000000000000000000001010000); assign _zz_254_ = ((decode_INSTRUCTION & _zz_261_) == (32'b00000000000000000001000001010000)); assign _zz_255_ = ((decode_INSTRUCTION & _zz_262_) == (32'b00000000000000000010000001010000)); assign _zz_256_ = {(_zz_263_ == _zz_264_),{_zz_265_,_zz_266_}}; assign _zz_257_ = (3'b000); assign _zz_258_ = (_zz_104_ != (1'b0)); assign _zz_259_ = (_zz_267_ != (1'b0)); assign _zz_260_ = {(_zz_268_ != _zz_269_),{_zz_270_,{_zz_271_,_zz_272_}}}; assign _zz_261_ = (32'b00000000000000000001000001010000); assign _zz_262_ = (32'b00000000000000000010000001010000); assign _zz_263_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); assign _zz_264_ = (32'b00000000000000000000000001000000); assign _zz_265_ = ((decode_INSTRUCTION & (32'b01000000000000000000000000110000)) == (32'b01000000000000000000000000110000)); assign _zz_266_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000)); assign _zz_267_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000101000000010000)); assign _zz_268_ = {(_zz_273_ == _zz_274_),(_zz_275_ == _zz_276_)}; assign _zz_269_ = (2'b00); assign _zz_270_ = ({_zz_103_,_zz_277_} != (2'b00)); assign _zz_271_ = ({_zz_278_,_zz_279_} != (2'b00)); assign _zz_272_ = {(_zz_280_ != _zz_281_),{_zz_282_,_zz_283_}}; assign _zz_273_ = (decode_INSTRUCTION & (32'b01000000000000000011000001010100)); assign _zz_274_ = (32'b01000000000000000001000000010000); assign _zz_275_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); assign _zz_276_ = (32'b00000000000000000001000000010000); assign _zz_277_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); assign _zz_278_ = _zz_103_; assign _zz_279_ = _zz_102_; assign _zz_280_ = {((decode_INSTRUCTION & _zz_284_) == (32'b00000000000000000000000000000000)),{(_zz_285_ == _zz_286_),{_zz_101_,_zz_287_}}}; assign _zz_281_ = (4'b0000); assign _zz_282_ = ({(_zz_288_ == _zz_289_),(_zz_290_ == _zz_291_)} != (2'b00)); assign _zz_283_ = (((decode_INSTRUCTION & _zz_292_) == (32'b00000000000000000000000000000000)) != (1'b0)); assign _zz_284_ = (32'b00000000000000000000000001000100); assign _zz_285_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); assign _zz_286_ = (32'b00000000000000000000000000000000); assign _zz_287_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000)); assign _zz_288_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); assign _zz_289_ = (32'b00000000000000000000000000100000); assign _zz_290_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); assign _zz_291_ = (32'b00000000000000000000000000100000); assign _zz_292_ = (32'b00000000000000000000000001010000); always @ (posedge clk) begin if(_zz_39_) begin RegFilePlugin_regFile[writeBack_RegFilePlugin_regFileWrite_payload_address] <= writeBack_RegFilePlugin_regFileWrite_payload_data; end end always @ (posedge clk) begin if(_zz_201_) begin _zz_140_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin if(_zz_202_) begin _zz_141_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( .io_push_valid(_zz_138_), .io_push_ready(_zz_142_), .io_push_payload_error(iBus_rsp_payload_error), .io_push_payload_inst(iBus_rsp_payload_inst), .io_pop_valid(_zz_143_), .io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready), .io_pop_payload_error(_zz_144_), .io_pop_payload_inst(_zz_145_), .io_flush(_zz_139_), .io_occupancy(_zz_146_), .clk(clk), .reset(reset) ); assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = _zz_68_; assign decode_ALU_BITWISE_CTRL = _zz_1_; assign _zz_2_ = _zz_3_; assign decode_CSR_WRITE_OPCODE = _zz_62_; assign decode_SRC_USE_SUB_LESS = _zz_51_; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; assign decode_BYPASSABLE_MEMORY_STAGE = _zz_46_; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign execute_REGFILE_WRITE_DATA = _zz_35_; assign _zz_4_ = _zz_5_; assign _zz_6_ = _zz_7_; assign decode_ENV_CTRL = _zz_8_; assign _zz_9_ = _zz_10_; assign decode_SRC2 = _zz_30_; assign memory_PC = execute_to_memory_PC; assign decode_SHIFT_CTRL = _zz_11_; assign _zz_12_ = _zz_13_; assign execute_BRANCH_CALC = _zz_20_; assign memory_MEMORY_READ_DATA = _zz_65_; assign decode_SRC1 = _zz_33_; assign execute_BRANCH_DO = _zz_22_; assign decode_CSR_READ_OPCODE = _zz_61_; assign decode_BRANCH_CTRL = _zz_14_; assign _zz_15_ = _zz_16_; assign decode_RS1 = _zz_41_; assign decode_IS_CSR = _zz_50_; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = _zz_66_; assign decode_ALU_CTRL = _zz_17_; assign _zz_18_ = _zz_19_; assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_52_; assign decode_MEMORY_ENABLE = _zz_57_; assign decode_SRC_LESS_UNSIGNED = _zz_44_; assign decode_RS2 = _zz_40_; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_CTRL = _zz_21_; assign decode_RS2_USE = _zz_56_; assign decode_RS1_USE = _zz_55_; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign execute_SHIFT_CTRL = _zz_23_; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; assign _zz_27_ = decode_PC; assign _zz_28_ = decode_RS2; assign decode_SRC2_CTRL = _zz_29_; assign _zz_31_ = decode_RS1; assign decode_SRC1_CTRL = _zz_32_; assign execute_SRC_ADD_SUB = _zz_26_; assign execute_SRC_LESS = _zz_24_; assign execute_ALU_CTRL = _zz_34_; assign execute_SRC2 = decode_to_execute_SRC2; assign execute_ALU_BITWISE_CTRL = _zz_36_; assign _zz_37_ = writeBack_INSTRUCTION; assign _zz_38_ = writeBack_REGFILE_WRITE_VALID; always @ (*) begin _zz_39_ = 1'b0; if(writeBack_RegFilePlugin_regFileWrite_valid)begin _zz_39_ = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = _zz_71_; always @ (*) begin decode_REGFILE_WRITE_VALID = _zz_45_; if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin decode_REGFILE_WRITE_VALID = 1'b0; end end always @ (*) begin _zz_58_ = execute_REGFILE_WRITE_DATA; execute_arbitration_haltItself = 1'b0; if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)))begin execute_arbitration_haltItself = 1'b1; end if((execute_arbitration_isValid && execute_IS_CSR))begin _zz_58_ = execute_CsrPlugin_readData; if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end end if(_zz_147_)begin _zz_58_ = _zz_122_; if(_zz_148_)begin if(! execute_LightShifterPlugin_done) begin execute_arbitration_haltItself = 1'b1; end end end end assign execute_SRC1 = decode_to_execute_SRC1; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; assign memory_ENV_CTRL = _zz_59_; assign execute_ENV_CTRL = _zz_60_; assign writeBack_ENV_CTRL = _zz_63_; always @ (*) begin _zz_64_ = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_64_ = writeBack_DBusSimplePlugin_rspFormated; end end assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; assign execute_RS2 = decode_to_execute_RS2; assign execute_SRC_ADD = _zz_25_; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_ALIGNEMENT_FAULT = 1'b0; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; always @ (*) begin _zz_67_ = memory_FORMAL_PC_NEXT; if(_zz_75_)begin _zz_67_ = _zz_76_; end end assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; assign decode_PC = _zz_70_; assign decode_INSTRUCTION = _zz_69_; assign decode_arbitration_haltItself = 1'b0; always @ (*) begin decode_arbitration_haltByOther = 1'b0; if((CsrPlugin_interrupt && decode_arbitration_isValid))begin decode_arbitration_haltByOther = 1'b1; end if(({(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))} != (2'b00)))begin decode_arbitration_haltByOther = 1'b1; end if((decode_arbitration_isValid && (_zz_123_ || _zz_124_)))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; if(decode_arbitration_isFlushed)begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushAll = 1'b0; assign decode_arbitration_redoIt = 1'b0; assign execute_arbitration_haltByOther = 1'b0; always @ (*) begin execute_arbitration_removeIt = 1'b0; if(execute_arbitration_isFlushed)begin execute_arbitration_removeIt = 1'b1; end end always @ (*) begin execute_arbitration_flushAll = 1'b0; if(_zz_75_)begin execute_arbitration_flushAll = 1'b1; end end assign execute_arbitration_redoIt = 1'b0; always @ (*) begin memory_arbitration_haltItself = 1'b0; if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin memory_arbitration_haltItself = 1'b1; end end assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; if(memory_arbitration_isFlushed)begin memory_arbitration_removeIt = 1'b1; end end always @ (*) begin memory_arbitration_flushAll = 1'b0; _zz_73_ = 1'b0; _zz_74_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); if(_zz_149_)begin _zz_73_ = 1'b1; _zz_74_ = {CsrPlugin_mtvec_base,(2'b00)}; memory_arbitration_flushAll = 1'b1; end if(_zz_150_)begin _zz_74_ = CsrPlugin_mepc; _zz_73_ = 1'b1; memory_arbitration_flushAll = 1'b1; end end assign memory_arbitration_redoIt = 1'b0; assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; always @ (*) begin writeBack_arbitration_removeIt = 1'b0; if(writeBack_arbitration_isFlushed)begin writeBack_arbitration_removeIt = 1'b1; end end assign writeBack_arbitration_flushAll = 1'b0; assign writeBack_arbitration_redoIt = 1'b0; assign _zz_72_ = 1'b0; assign IBusSimplePlugin_jump_pcLoad_valid = (_zz_73_ || _zz_75_); assign _zz_77_ = {_zz_75_,_zz_73_}; assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_155_[0] ? _zz_74_ : _zz_76_); assign _zz_78_ = (! 1'b0); assign IBusSimplePlugin_fetchPc_output_valid = (IBusSimplePlugin_fetchPc_preOutput_valid && _zz_78_); assign IBusSimplePlugin_fetchPc_preOutput_ready = (IBusSimplePlugin_fetchPc_output_ready && _zz_78_); assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_preOutput_payload; always @ (*) begin IBusSimplePlugin_fetchPc_propagatePc = 1'b0; if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_iBusRsp_stages_1_input_ready))begin IBusSimplePlugin_fetchPc_propagatePc = 1'b1; end end always @ (*) begin IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_158_); IBusSimplePlugin_fetchPc_samplePcNext = 1'b0; if(IBusSimplePlugin_fetchPc_propagatePc)begin IBusSimplePlugin_fetchPc_samplePcNext = 1'b1; end if(IBusSimplePlugin_jump_pcLoad_valid)begin IBusSimplePlugin_fetchPc_samplePcNext = 1'b1; IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; end if(_zz_151_)begin IBusSimplePlugin_fetchPc_samplePcNext = 1'b1; end IBusSimplePlugin_fetchPc_pc[0] = 1'b0; IBusSimplePlugin_fetchPc_pc[1] = 1'b0; end assign IBusSimplePlugin_fetchPc_preOutput_valid = _zz_79_; assign IBusSimplePlugin_fetchPc_preOutput_payload = IBusSimplePlugin_fetchPc_pc; assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; end end assign _zz_80_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt); assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_80_); assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_80_); assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; assign _zz_81_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt); assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_81_); assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_81_); assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_82_; assign _zz_82_ = ((1'b0 && (! _zz_83_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); assign _zz_83_ = _zz_84_; assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_83_; assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; always @ (*) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b1; if(IBusSimplePlugin_injector_decodeInput_valid)begin IBusSimplePlugin_iBusRsp_readyForError = 1'b0; end end assign IBusSimplePlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); assign IBusSimplePlugin_injector_decodeInput_valid = _zz_85_; assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_86_; assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_87_; assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_88_; assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_89_; assign _zz_71_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_raw); assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved)); assign _zz_70_ = IBusSimplePlugin_injector_decodeInput_payload_pc; assign _zz_69_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; assign _zz_68_ = (decode_PC + (32'b00000000000000000000000000000100)); assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; assign IBusSimplePlugin_pendingCmdNext = (_zz_159_ - _zz_163_); assign IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (3'b111))); assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_0_input_payload[31 : 2],(2'b00)}; assign _zz_138_ = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)))); assign _zz_139_ = (IBusSimplePlugin_jump_pcLoad_valid || _zz_72_); assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = _zz_143_; assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = _zz_144_; assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = _zz_145_; assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; always @ (*) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; end end assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; assign IBusSimplePlugin_rspJoin_issueDetected = 1'b0; assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid); assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); assign _zz_90_ = (! IBusSimplePlugin_rspJoin_issueDetected); assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_inputBeforeStage_ready && _zz_90_); assign IBusSimplePlugin_iBusRsp_inputBeforeStage_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_90_); assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_raw = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; assign execute_DBusSimplePlugin_cmdSent = 1'b0; assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)); assign dBus_cmd_payload_wr = execute_INSTRUCTION[5]; assign dBus_cmd_payload_address = execute_SRC_ADD; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin _zz_91_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin _zz_91_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin _zz_91_ = execute_RS2[31 : 0]; end endcase end assign dBus_cmd_payload_data = _zz_91_; assign _zz_66_ = dBus_cmd_payload_address[1 : 0]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin _zz_92_ = (4'b0001); end 2'b01 : begin _zz_92_ = (4'b0011); end default : begin _zz_92_ = (4'b1111); end endcase end assign execute_DBusSimplePlugin_formalMask = (_zz_92_ <<< dBus_cmd_payload_address[1 : 0]); assign _zz_65_ = dBus_rsp_data; always @ (*) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; end 2'b10 : begin writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; end 2'b11 : begin writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; end default : begin end endcase end assign _zz_93_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); always @ (*) begin _zz_94_[31] = _zz_93_; _zz_94_[30] = _zz_93_; _zz_94_[29] = _zz_93_; _zz_94_[28] = _zz_93_; _zz_94_[27] = _zz_93_; _zz_94_[26] = _zz_93_; _zz_94_[25] = _zz_93_; _zz_94_[24] = _zz_93_; _zz_94_[23] = _zz_93_; _zz_94_[22] = _zz_93_; _zz_94_[21] = _zz_93_; _zz_94_[20] = _zz_93_; _zz_94_[19] = _zz_93_; _zz_94_[18] = _zz_93_; _zz_94_[17] = _zz_93_; _zz_94_[16] = _zz_93_; _zz_94_[15] = _zz_93_; _zz_94_[14] = _zz_93_; _zz_94_[13] = _zz_93_; _zz_94_[12] = _zz_93_; _zz_94_[11] = _zz_93_; _zz_94_[10] = _zz_93_; _zz_94_[9] = _zz_93_; _zz_94_[8] = _zz_93_; _zz_94_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; end assign _zz_95_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); always @ (*) begin _zz_96_[31] = _zz_95_; _zz_96_[30] = _zz_95_; _zz_96_[29] = _zz_95_; _zz_96_[28] = _zz_95_; _zz_96_[27] = _zz_95_; _zz_96_[26] = _zz_95_; _zz_96_[25] = _zz_95_; _zz_96_[24] = _zz_95_; _zz_96_[23] = _zz_95_; _zz_96_[22] = _zz_95_; _zz_96_[21] = _zz_95_; _zz_96_[20] = _zz_95_; _zz_96_[19] = _zz_95_; _zz_96_[18] = _zz_95_; _zz_96_[17] = _zz_95_; _zz_96_[16] = _zz_95_; _zz_96_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; end always @ (*) begin case(_zz_152_) 2'b00 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_94_; end 2'b01 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_96_; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; end endcase end assign CsrPlugin_misa_base = (2'b01); assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); assign CsrPlugin_mtvec_mode = (2'b00); assign CsrPlugin_mtvec_base = (30'b000000000000000000000000001000); assign CsrPlugin_medeleg = (32'b00000000000000000000000000000000); assign CsrPlugin_mideleg = (32'b00000000000000000000000000000000); assign _zz_97_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); assign _zz_98_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); assign _zz_99_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); always @ (*) begin CsrPlugin_interrupt = 1'b0; CsrPlugin_interruptCode = (4'bxxxx); CsrPlugin_interruptTargetPrivilege = (2'bxx); if(CsrPlugin_mstatus_MIE)begin if(((_zz_97_ || _zz_98_) || _zz_99_))begin CsrPlugin_interrupt = 1'b1; end if(_zz_97_)begin CsrPlugin_interruptCode = (4'b0111); CsrPlugin_interruptTargetPrivilege = (2'b11); end if(_zz_98_)begin CsrPlugin_interruptCode = (4'b0011); CsrPlugin_interruptTargetPrivilege = (2'b11); end if(_zz_99_)begin CsrPlugin_interruptCode = (4'b1011); CsrPlugin_interruptTargetPrivilege = (2'b11); end end if((! 1'b1))begin CsrPlugin_interrupt = 1'b0; end end assign CsrPlugin_exception = 1'b0; assign CsrPlugin_lastStageWasWfi = 1'b0; always @ (*) begin CsrPlugin_pipelineLiberator_done = ((! ((execute_arbitration_isValid || memory_arbitration_isValid) || writeBack_arbitration_isValid)) && IBusSimplePlugin_injector_nextPcCalc_0); if(CsrPlugin_hadException)begin CsrPlugin_pipelineLiberator_done = 1'b0; end end assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); assign CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; assign CsrPlugin_trapCause = CsrPlugin_interruptCode; assign contextSwitching = _zz_73_; assign _zz_62_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); assign _zz_61_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); case(execute_CsrPlugin_csrAddress) 12'b001100000000 : begin execute_CsrPlugin_illegalAccess = 1'b0; execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; end 12'b001101000100 : begin execute_CsrPlugin_illegalAccess = 1'b0; execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; end 12'b001100000100 : begin execute_CsrPlugin_illegalAccess = 1'b0; execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; end 12'b001101000010 : begin if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; end default : begin end endcase if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin execute_CsrPlugin_illegalAccess = 1'b0; end end always @ (*) begin execute_CsrPlugin_illegalInstruction = 1'b0; if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin if((execute_INSTRUCTION[29 : 28] != CsrPlugin_privilege))begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); always @ (*) begin case(_zz_154_) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end default : begin execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readData & (~ execute_SRC1)) : (execute_CsrPlugin_readData | execute_SRC1)); end endcase end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign _zz_101_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)); assign _zz_102_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); assign _zz_103_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); assign _zz_104_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); assign _zz_105_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); assign _zz_106_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); assign _zz_100_ = {({_zz_105_,_zz_106_} != (2'b00)),{({_zz_203_,_zz_106_} != (2'b00)),{({_zz_204_,_zz_205_} != (2'b00)),{(_zz_206_ != _zz_207_),{_zz_208_,{_zz_209_,_zz_210_}}}}}}; assign _zz_57_ = _zz_168_[0]; assign _zz_56_ = _zz_169_[0]; assign _zz_55_ = _zz_170_[0]; assign _zz_107_ = _zz_100_[4 : 3]; assign _zz_54_ = _zz_107_; assign _zz_108_ = _zz_100_[6 : 5]; assign _zz_53_ = _zz_108_; assign _zz_52_ = _zz_171_[0]; assign _zz_51_ = _zz_172_[0]; assign _zz_50_ = _zz_173_[0]; assign _zz_109_ = _zz_100_[10 : 10]; assign _zz_49_ = _zz_109_; assign _zz_110_ = _zz_100_[12 : 11]; assign _zz_48_ = _zz_110_; assign _zz_111_ = _zz_100_[14 : 13]; assign _zz_47_ = _zz_111_; assign _zz_46_ = _zz_174_[0]; assign _zz_45_ = _zz_175_[0]; assign _zz_44_ = _zz_176_[0]; assign _zz_112_ = _zz_100_[20 : 19]; assign _zz_43_ = _zz_112_; assign _zz_113_ = _zz_100_[22 : 21]; assign _zz_42_ = _zz_113_; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; assign decode_RegFilePlugin_rs1Data = _zz_140_; assign decode_RegFilePlugin_rs2Data = _zz_141_; assign _zz_41_ = decode_RegFilePlugin_rs1Data; assign _zz_40_ = decode_RegFilePlugin_rs2Data; always @ (*) begin writeBack_RegFilePlugin_regFileWrite_valid = (_zz_38_ && writeBack_arbitration_isFiring); if(_zz_114_)begin writeBack_RegFilePlugin_regFileWrite_valid = 1'b1; end end assign writeBack_RegFilePlugin_regFileWrite_payload_address = _zz_37_[11 : 7]; assign writeBack_RegFilePlugin_regFileWrite_payload_data = _zz_64_; always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); end default : begin execute_IntAluPlugin_bitwise = execute_SRC1; end endcase end always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin _zz_115_ = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin _zz_115_ = {31'd0, _zz_177_}; end default : begin _zz_115_ = execute_SRC_ADD_SUB; end endcase end assign _zz_35_ = _zz_115_; always @ (*) begin case(decode_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin _zz_116_ = _zz_31_; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin _zz_116_ = {29'd0, _zz_178_}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_116_ = {decode_INSTRUCTION[31 : 12],(12'b000000000000)}; end default : begin _zz_116_ = {27'd0, _zz_179_}; end endcase end assign _zz_33_ = _zz_116_; assign _zz_117_ = _zz_180_[11]; always @ (*) begin _zz_118_[19] = _zz_117_; _zz_118_[18] = _zz_117_; _zz_118_[17] = _zz_117_; _zz_118_[16] = _zz_117_; _zz_118_[15] = _zz_117_; _zz_118_[14] = _zz_117_; _zz_118_[13] = _zz_117_; _zz_118_[12] = _zz_117_; _zz_118_[11] = _zz_117_; _zz_118_[10] = _zz_117_; _zz_118_[9] = _zz_117_; _zz_118_[8] = _zz_117_; _zz_118_[7] = _zz_117_; _zz_118_[6] = _zz_117_; _zz_118_[5] = _zz_117_; _zz_118_[4] = _zz_117_; _zz_118_[3] = _zz_117_; _zz_118_[2] = _zz_117_; _zz_118_[1] = _zz_117_; _zz_118_[0] = _zz_117_; end assign _zz_119_ = _zz_181_[11]; always @ (*) begin _zz_120_[19] = _zz_119_; _zz_120_[18] = _zz_119_; _zz_120_[17] = _zz_119_; _zz_120_[16] = _zz_119_; _zz_120_[15] = _zz_119_; _zz_120_[14] = _zz_119_; _zz_120_[13] = _zz_119_; _zz_120_[12] = _zz_119_; _zz_120_[11] = _zz_119_; _zz_120_[10] = _zz_119_; _zz_120_[9] = _zz_119_; _zz_120_[8] = _zz_119_; _zz_120_[7] = _zz_119_; _zz_120_[6] = _zz_119_; _zz_120_[5] = _zz_119_; _zz_120_[4] = _zz_119_; _zz_120_[3] = _zz_119_; _zz_120_[2] = _zz_119_; _zz_120_[1] = _zz_119_; _zz_120_[0] = _zz_119_; end always @ (*) begin case(decode_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin _zz_121_ = _zz_28_; end `Src2CtrlEnum_defaultEncoding_IMI : begin _zz_121_ = {_zz_118_,decode_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin _zz_121_ = {_zz_120_,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; end default : begin _zz_121_ = _zz_27_; end endcase end assign _zz_30_ = _zz_121_; assign execute_SrcPlugin_addSub = _zz_182_; assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign _zz_26_ = execute_SrcPlugin_addSub; assign _zz_25_ = execute_SrcPlugin_addSub; assign _zz_24_ = execute_SrcPlugin_less; assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin _zz_122_ = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin _zz_122_ = _zz_190_; end endcase end always @ (*) begin _zz_123_ = 1'b0; _zz_124_ = 1'b0; if(_zz_126_)begin if((_zz_127_ == decode_INSTRUCTION[19 : 15]))begin _zz_123_ = 1'b1; end if((_zz_127_ == decode_INSTRUCTION[24 : 20]))begin _zz_124_ = 1'b1; end end if((writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID))begin if((1'b1 || (! 1'b1)))begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin _zz_123_ = 1'b1; end if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin _zz_124_ = 1'b1; end end end if((memory_arbitration_isValid && memory_REGFILE_WRITE_VALID))begin if((1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)))begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin _zz_123_ = 1'b1; end if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin _zz_124_ = 1'b1; end end end if((execute_arbitration_isValid && execute_REGFILE_WRITE_VALID))begin if((1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)))begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin _zz_123_ = 1'b1; end if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin _zz_124_ = 1'b1; end end end if((! decode_RS1_USE))begin _zz_123_ = 1'b0; end if((! decode_RS2_USE))begin _zz_124_ = 1'b0; end end assign _zz_125_ = (_zz_38_ && writeBack_arbitration_isFiring); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); assign _zz_128_ = execute_INSTRUCTION[14 : 12]; always @ (*) begin if((_zz_128_ == (3'b000))) begin _zz_129_ = execute_BranchPlugin_eq; end else if((_zz_128_ == (3'b001))) begin _zz_129_ = (! execute_BranchPlugin_eq); end else if((((_zz_128_ & (3'b101)) == (3'b101)))) begin _zz_129_ = (! execute_SRC_LESS); end else begin _zz_129_ = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin _zz_130_ = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin _zz_130_ = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin _zz_130_ = 1'b1; end default : begin _zz_130_ = _zz_129_; end endcase end assign _zz_22_ = _zz_130_; assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); assign _zz_131_ = _zz_192_[19]; always @ (*) begin _zz_132_[10] = _zz_131_; _zz_132_[9] = _zz_131_; _zz_132_[8] = _zz_131_; _zz_132_[7] = _zz_131_; _zz_132_[6] = _zz_131_; _zz_132_[5] = _zz_131_; _zz_132_[4] = _zz_131_; _zz_132_[3] = _zz_131_; _zz_132_[2] = _zz_131_; _zz_132_[1] = _zz_131_; _zz_132_[0] = _zz_131_; end assign _zz_133_ = _zz_193_[11]; always @ (*) begin _zz_134_[19] = _zz_133_; _zz_134_[18] = _zz_133_; _zz_134_[17] = _zz_133_; _zz_134_[16] = _zz_133_; _zz_134_[15] = _zz_133_; _zz_134_[14] = _zz_133_; _zz_134_[13] = _zz_133_; _zz_134_[12] = _zz_133_; _zz_134_[11] = _zz_133_; _zz_134_[10] = _zz_133_; _zz_134_[9] = _zz_133_; _zz_134_[8] = _zz_133_; _zz_134_[7] = _zz_133_; _zz_134_[6] = _zz_133_; _zz_134_[5] = _zz_133_; _zz_134_[4] = _zz_133_; _zz_134_[3] = _zz_133_; _zz_134_[2] = _zz_133_; _zz_134_[1] = _zz_133_; _zz_134_[0] = _zz_133_; end assign _zz_135_ = _zz_194_[11]; always @ (*) begin _zz_136_[18] = _zz_135_; _zz_136_[17] = _zz_135_; _zz_136_[16] = _zz_135_; _zz_136_[15] = _zz_135_; _zz_136_[14] = _zz_135_; _zz_136_[13] = _zz_135_; _zz_136_[12] = _zz_135_; _zz_136_[11] = _zz_135_; _zz_136_[10] = _zz_135_; _zz_136_[9] = _zz_135_; _zz_136_[8] = _zz_135_; _zz_136_[7] = _zz_135_; _zz_136_[6] = _zz_135_; _zz_136_[5] = _zz_135_; _zz_136_[4] = _zz_135_; _zz_136_[3] = _zz_135_; _zz_136_[2] = _zz_135_; _zz_136_[1] = _zz_135_; _zz_136_[0] = _zz_135_; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin _zz_137_ = {{_zz_132_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin _zz_137_ = {_zz_134_,execute_INSTRUCTION[31 : 20]}; end default : begin _zz_137_ = {{_zz_136_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end assign execute_BranchPlugin_branch_src2 = _zz_137_; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign _zz_20_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign _zz_75_ = ((memory_arbitration_isValid && (! memory_arbitration_isStuckByOthers)) && memory_BRANCH_DO); assign _zz_76_ = memory_BRANCH_CALC; assign _zz_29_ = _zz_54_; assign _zz_19_ = decode_ALU_CTRL; assign _zz_17_ = _zz_47_; assign _zz_34_ = decode_to_execute_ALU_CTRL; assign _zz_16_ = decode_BRANCH_CTRL; assign _zz_14_ = _zz_48_; assign _zz_21_ = decode_to_execute_BRANCH_CTRL; assign _zz_32_ = _zz_42_; assign _zz_13_ = decode_SHIFT_CTRL; assign _zz_11_ = _zz_53_; assign _zz_23_ = decode_to_execute_SHIFT_CTRL; assign _zz_10_ = decode_ENV_CTRL; assign _zz_7_ = execute_ENV_CTRL; assign _zz_5_ = memory_ENV_CTRL; assign _zz_8_ = _zz_49_; assign _zz_60_ = decode_to_execute_ENV_CTRL; assign _zz_59_ = execute_to_memory_ENV_CTRL; assign _zz_63_ = memory_to_writeBack_ENV_CTRL; assign _zz_3_ = decode_ALU_BITWISE_CTRL; assign _zz_1_ = _zz_43_; assign _zz_36_ = decode_to_execute_ALU_BITWISE_CTRL; assign decode_arbitration_isFlushed = (((decode_arbitration_flushAll || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); assign execute_arbitration_isFlushed = ((execute_arbitration_flushAll || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); assign memory_arbitration_isFlushed = (memory_arbitration_flushAll || writeBack_arbitration_flushAll); assign writeBack_arbitration_isFlushed = writeBack_arbitration_flushAll; assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (posedge clk or posedge reset) begin if (reset) begin CsrPlugin_privilege <= (2'b11); IBusSimplePlugin_fetchPc_pcReg <= (32'b10000000000000000000000000000000); IBusSimplePlugin_fetchPc_inc <= 1'b0; _zz_79_ <= 1'b0; _zz_84_ <= 1'b0; _zz_85_ <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_0 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_1 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_2 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_3 <= 1'b0; IBusSimplePlugin_injector_decodeRemoved <= 1'b0; IBusSimplePlugin_pendingCmd <= (3'b000); IBusSimplePlugin_rspJoin_discardCounter <= (3'b000); CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= (2'b11); CsrPlugin_mip_MEIP <= 1'b0; CsrPlugin_mip_MTIP <= 1'b0; CsrPlugin_mip_MSIP <= 1'b0; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; CsrPlugin_hadException <= 1'b0; _zz_114_ <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; _zz_126_ <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); end else begin if(IBusSimplePlugin_fetchPc_propagatePc)begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end if(IBusSimplePlugin_jump_pcLoad_valid)begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end if(_zz_151_)begin IBusSimplePlugin_fetchPc_inc <= 1'b1; end if(IBusSimplePlugin_fetchPc_samplePcNext)begin IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; end _zz_79_ <= 1'b1; if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin _zz_84_ <= 1'b0; end if(_zz_82_)begin _zz_84_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid; end if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin _zz_85_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin _zz_85_ <= 1'b0; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_nextPcCalc_0 <= 1'b0; end if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin IBusSimplePlugin_injector_nextPcCalc_0 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_nextPcCalc_0 <= 1'b0; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_nextPcCalc_1 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusSimplePlugin_injector_nextPcCalc_1 <= IBusSimplePlugin_injector_nextPcCalc_0; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_nextPcCalc_1 <= 1'b0; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_nextPcCalc_2 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusSimplePlugin_injector_nextPcCalc_2 <= IBusSimplePlugin_injector_nextPcCalc_1; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_nextPcCalc_2 <= 1'b0; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_nextPcCalc_3 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusSimplePlugin_injector_nextPcCalc_3 <= IBusSimplePlugin_injector_nextPcCalc_2; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_nextPcCalc_3 <= 1'b0; end if(decode_arbitration_removeIt)begin IBusSimplePlugin_injector_decodeRemoved <= 1'b1; end if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_injector_decodeRemoved <= 1'b0; end IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext; IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_165_); if((IBusSimplePlugin_jump_pcLoad_valid || _zz_72_))begin IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_167_); end CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_hadException <= CsrPlugin_exception; if(_zz_149_)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; end default : begin end endcase end if(_zz_150_)begin case(_zz_153_) 2'b11 : begin CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPP <= (2'b00); CsrPlugin_mstatus_MPIE <= 1'b1; CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; end default : begin end endcase end _zz_114_ <= 1'b0; if(_zz_147_)begin if(_zz_148_)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; end end end if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end _zz_126_ <= _zz_125_; if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin execute_arbitration_isValid <= decode_arbitration_isValid; end if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin memory_arbitration_isValid <= 1'b0; end if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin memory_arbitration_isValid <= execute_arbitration_isValid; end if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin writeBack_arbitration_isValid <= 1'b0; end if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end case(execute_CsrPlugin_csrAddress) 12'b001100000000 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; CsrPlugin_mstatus_MPIE <= _zz_195_[0]; CsrPlugin_mstatus_MIE <= _zz_196_[0]; end end 12'b001101000100 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mip_MSIP <= _zz_197_[0]; end end 12'b001100000100 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mie_MEIE <= _zz_198_[0]; CsrPlugin_mie_MTIE <= _zz_199_[0]; CsrPlugin_mie_MSIE <= _zz_200_[0]; end end 12'b001101000010 : begin end default : begin end endcase end end always @ (posedge clk) begin if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin _zz_86_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; _zz_87_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; _zz_88_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_raw; _zz_89_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; end if(IBusSimplePlugin_injector_decodeInput_ready)begin IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_raw; end if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); end if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_INSTRUCTION[5])) && writeBack_arbitration_isStuck))) begin $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); end CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); end if((CsrPlugin_exception || CsrPlugin_interruptJump))begin case(CsrPlugin_privilege) 2'b11 : begin CsrPlugin_mepc <= decode_PC; end default : begin end endcase end if(_zz_149_)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; end default : begin end endcase end if(_zz_147_)begin if(_zz_148_)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); end end if(_zz_125_)begin _zz_127_ <= _zz_37_[11 : 7]; end if((! execute_arbitration_isStuck))begin decode_to_execute_RS2 <= _zz_28_; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end if((! memory_arbitration_isStuck))begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end if((! execute_arbitration_isStuck))begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end if((! execute_arbitration_isStuck))begin decode_to_execute_ALU_CTRL <= _zz_18_; end if((! memory_arbitration_isStuck))begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_CSR <= decode_IS_CSR; end if((! execute_arbitration_isStuck))begin decode_to_execute_RS1 <= _zz_31_; end if((! execute_arbitration_isStuck))begin decode_to_execute_BRANCH_CTRL <= _zz_15_; end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end if((! memory_arbitration_isStuck))begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC1 <= decode_SRC1; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end if((! memory_arbitration_isStuck))begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end if((! execute_arbitration_isStuck))begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end if((! memory_arbitration_isStuck))begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end if((! execute_arbitration_isStuck))begin decode_to_execute_SHIFT_CTRL <= _zz_12_; end if((! execute_arbitration_isStuck))begin decode_to_execute_PC <= _zz_27_; end if((! memory_arbitration_isStuck))begin execute_to_memory_PC <= execute_PC; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_PC <= memory_PC; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC2 <= decode_SRC2; end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end if((! memory_arbitration_isStuck))begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end if((! execute_arbitration_isStuck))begin decode_to_execute_ENV_CTRL <= _zz_9_; end if((! memory_arbitration_isStuck))begin execute_to_memory_ENV_CTRL <= _zz_6_; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_ENV_CTRL <= _zz_4_; end if((! memory_arbitration_isStuck))begin execute_to_memory_REGFILE_WRITE_DATA <= _zz_58_; end if((! execute_arbitration_isStuck))begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end if((! memory_arbitration_isStuck))begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end if((! execute_arbitration_isStuck))begin decode_to_execute_ALU_BITWISE_CTRL <= _zz_2_; end if((! execute_arbitration_isStuck))begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end if((! memory_arbitration_isStuck))begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_FORMAL_PC_NEXT <= _zz_67_; end end endmodule Jeszcze nie próbowałem na jego podstawie wygenerować pliku konfiguracyjnego dla układu FPGA (w ISE czy Vivado), więc nie wiem czy układ syntetyzuje się poprawnie. Takie próby przeprowadzę w najbliższym czasie. Pozdrawiam VexRiscv.v.zip Pierwsze próby syntezy projektu w ISE 14.7 (Webpack Linux) już wykonane. Dla płytki FPGA Elbert V2 ze Spartanem 3 projekt procesora jest za duży (zabrakło tylko pinów I/O inne zasoby są wystarczające), natomiast dla płytki Mimas V2 (ze Spartanem 6) synteza i implementacja zakończyły się bez błędów. Jeśli komuś chciałoby się zrobić multipleksery na 32-bitowe magistrale to układ by się prawdopodobnie zmieścił na Spartana 3 z płytki Elbert V2 - bo po prostu zabrakło pinów I/O. Muszę gdzieś w dokumentacji znaleźć po co temu CPU jest potrzebnych aż 5 32-bitowych magistral? Wygenerowałem też wydajniejszą wersję "Full" tego procesora (cokolwiek to oznacza, bo nie jestem pewien jakie detale architektury ma zaimplementowane). Zamieszczam ją w nastepnym archiwum zip. VexRiscvFull.zip Syntezy tej wydajniejszej wersji chciałbym, dokonać na zestawie FPGA "CmodA7" z układem "Artix 7" Xilinxa: https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start?redirect=1id=cmod_a7/cm w Xilinx "Vivadfo 2018.2". Potem chciałbym przeprowadzić testy opisane na stronie projektu z użyciem symulatora "Verilator" (#Regression tests): https://github.com/SpinalHDL/VexRiscv Następnie zapoznać się z kompilatorem języka C i debuggerem dla "RiscV". W końcowej fazie chciałbym wygenerować CPU "VexRiscV" z parametrami jakie sobię założę (FPU, MMU, Cache, branch prediction). Dokonać syntezy układu na płytce FPGA (Artix 7) Vivado. I porobić eksperymenty z CPU uruchomioinoym na układzie FPGA. Gdyby z tych praktycznych prób z "RiscV" zaimplementowanym na układzie FPGA coś wyszło to jako ostatnią fazę eksperymentów chciałbym na nim uruchomić aplikację z "Free RTOS" oraz Linuxem dla tej architektury. Patrz linki: https://github.com/illustris/FreeRTOS-RISCV https://github.com/RISCV-on-Microsemi-FPGA/FreeRTOS https://riscv.org/software-tools/linux/ https://wiki.debian.org/RISC-V Właśnie zobaczyłem, że opisany na stronie projektu #Briey SoC: https://github.com/SpinalHDL/VexRiscv ma ładnie "obudowane" te szerokie magistrale, więc spróbuję go wygenerować i na nim przeprowadzić praktyczne próby na układzie FPGA. Patrz rysunek: Pozdrawiam Edytowano Grudzień 25, 2018 przez FlyingDutch 1 Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 26, 2018 Autor tematu Udostępnij Grudzień 26, 2018 (edytowany) Cześć, "RiscV" - tematu ciąg dalszy. Wygenerowałem "Briey SoC" (Oparty na Riscv) jest on praktycznie bardzo podobny do opisanego tutaj "Pinsec": https://spinalhdl.github.io/SpinalDoc/spinal/lib/pinsec/hardware/#introduction Jego zaletą w stosunku do "czystego" RiscV (VexRiscv) jest to, że ma zrobiony "most" pomiędzy magistralami "Riscv" a magistralą "Axi". Skutkuje to wygodniejszym wyprowadzeniem interfejsów dla pamięci RAM, GPIO, UART, Timer, VGA . Tutaj zamieszczam wygenerowany "Briey SoC" (plik: Briey.v) w Verilogu. Briey.zip Niestey porty A i B GPIO dla "Briey SoC" - każdy z dwóch portów GPIO zawiera trzy 32-bitowe magistrale: Patrz " module Briey" w pliku Briey.v: module Briey ( input io_asyncReset, input io_axiClk, input io_vgaClk, input io_jtag_tms, input io_jtag_tdi, output io_jtag_tdo, input io_jtag_tck, output [12:0] io_sdram_ADDR, output [1:0] io_sdram_BA, input [15:0] io_sdram_DQ_read, output [15:0] io_sdram_DQ_write, output io_sdram_DQ_writeEnable, output [1:0] io_sdram_DQM, output io_sdram_CASn, output io_sdram_CKE, output io_sdram_CSn, output io_sdram_RASn, output io_sdram_WEn, input [31:0] io_gpioA_read, output [31:0] io_gpioA_write, output [31:0] io_gpioA_writeEnable, input [31:0] io_gpioB_read, output [31:0] io_gpioB_write, output [31:0] io_gpioB_writeEnable, output io_uart_txd, input io_uart_rxd, output io_vga_vSync, output io_vga_hSync, output io_vga_colorEn, output [4:0] io_vga_color_r, output [5:0] io_vga_color_g, output [4:0] io_vga_color_b, input io_timerExternal_clear, input io_timerExternal_tick, input io_coreInterrupt); To znacznie za długie magistrale, aby można je "wyprowadzić" na piny I/O płytki FPGA. Dlatego dokonałem pewnej korekty w pliku Verilog (Briey.v) opisującym nasz procesor, a mianowicie - usunałem całkowicie port GPIO B, a trzy magistarale GPIO A skróciłem z 32-bitów do 4. Patrz źródło: module Briey ( input io_asyncReset, input io_axiClk, input io_vgaClk, input io_jtag_tms, input io_jtag_tdi, output io_jtag_tdo, input io_jtag_tck, output [12:0] io_sdram_ADDR, output [1:0] io_sdram_BA, input [15:0] io_sdram_DQ_read, output [15:0] io_sdram_DQ_write, output io_sdram_DQ_writeEnable, output [1:0] io_sdram_DQM, output io_sdram_CASn, output io_sdram_CKE, output io_sdram_CSn, output io_sdram_RASn, output io_sdram_WEn, input [3:0] io_gpioA_read, output [3:0] io_gpioA_write, output [3:0] io_gpioA_writeEnable, //input [31:0] io_gpioB_read, //output [31:0] io_gpioB_write, //output [31:0] io_gpioB_writeEnable, output io_uart_txd, input io_uart_rxd, output io_vga_vSync, output io_vga_hSync, output io_vga_colorEn, output [4:0] io_vga_color_r, output [5:0] io_vga_color_g, output [4:0] io_vga_color_b, input io_timerExternal_clear, input io_timerExternal_tick, input io_coreInterrupt); Trzeba jeszcze było dokonać zmian w module: Apb3Gpio z(skrócić magistrale) i układ poprawnie się zsyntetyzował dla Spartana 6 z płytki FPGA "Mimas V2" (w ISE 14.7). Jak widać na schemacie (po syntezie) - w opisie portów procesora nie ma w ogóle "GPIO B" , a dla "GPIO A" trzy magistrale są skrócone z 32 do 4 bitów: W załączniku projekt dla Xilinx ISE 14.7 (Webpack) z SoC Briey (ze skróconymi magistralami GPIO - buduje się poprawnie dla Spartan6 - XC6SLX9😞 BrieySoC01.zip Teraz wypadałoby utworzyć "User constraint file" dla płytki FPGA Mimas V2, oraz zbudować/pobrać kompilator dla RiscV (co pewnie zajmie trochę czasu). W międzyczasie zainteresowani przykładami programów w języku C na "Briey SoC" mogą je znaleźć pod tym adresem: https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/briey A gotowe projekty FPGA (Quartus) z "Briey SoC" dla płytek Intela (DE1-SoC, DE0-Nano) można pobrać tutaj: http:// https://drive.google.com/drive/folders/0B-CqLXDTaMbKZGdJZlZ5THAxRTQ?usp=sharing Pozdrawiam Edytowano Grudzień 26, 2018 przez FlyingDutch 1 Cytuj Link do komentarza Share on other sites More sharing options...
Treker (Damian Szymański) Grudzień 27, 2018 Udostępnij Grudzień 27, 2018 @FlyingDutch, trochę nie moja tematyka, ale czytam Twoje wpisy cały czas - wygląda ciekawie 🙂 Dzięki, że znajdujesz czas, aby się tym publicznie podzielić! Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 27, 2018 Autor tematu Udostępnij Grudzień 27, 2018 Przed chwilą, Treker napisał: @FlyingDutch, trochę nie moja tematyka, ale czytam Twoje wpisy cały czas - wygląda ciekawie 🙂 Dzięki, że znajdujesz czas, aby się tym publicznie podzielić! Cześć Treker, takie rozpoznawanie nowego tematu, to jak podróż w nieznane - nigdy nie wiesz dokładnie gdzie Cię zaprowadzi. Najpierw jesteś przytłoczony ogromem nowych informacji, potem zaczynasz to jakoś porządkować, ale z pewnością nie jest to najbardziej efektywny sposób działania. Aktualnie jestem na etapie, że działa mi kompilator dla RiscV, ale nie wien jak z pliku binarnego programu (np. elf) po kompilacji wygenerować zawartość pamięci konfiguracji dla FPGA na której jest zaimplementowany RiscV. Pozdrawiam 1 Cytuj Link do komentarza Share on other sites More sharing options...
Treker (Damian Szymański) Grudzień 28, 2018 Udostępnij Grudzień 28, 2018 21 godzin temu, FlyingDutch napisał: Aktualnie jestem na etapie, że działa mi kompilator dla RiscV, ale nie wien jak z pliku binarnego programu (np. elf) po kompilacji wygenerować zawartość pamięci konfiguracji dla FPGA na której jest zaimplementowany RiscV. Niestety nie pomogę, bo zupełnie nie moja tematyka, ale kibicuję w szybkim rozwiązaniu problemu 😉 Cytuj Link do komentarza Share on other sites More sharing options...
FlyingDutch Grudzień 29, 2018 Autor tematu Udostępnij Grudzień 29, 2018 Cześć, kabel JTAG w połączeniu z "OpenOCD RiscV" powinien pozwolić mi "załadować" plik elf do pamięcvi SDRAM na płytce. No i właśnie kabel "JTAG-HS3", który kupiłem jakiś czas temu (a dopiero teraz miałem okazję wypróbować) nie działa. Sprawdzałem z trzema zestawami FPGA (różnymi). Oraz aplikacjami "Adept JTAG", "Xilinx Impact" i "Vivado". Nie mogę zmusić go do działania: jeśli podłączam kabel USB do JTAG'a, a z drugiej nie jest podłączony do płytki FPGA, to jest wykrywany przez aplikację. Jak tylko podłączam z drugiej strony układ "FPGA" (bądź pamięć SPI Flash), to zczytuje bzdury i pojawia się komunikat o błędzie konfiguracji. Ostatnio nic mi nie wychodzi i nie sprawia radości, chyba czas na jakiś kilkudniowy urlop (wyjazd), tylko, że przez Święta brak kasy 😪 Pozdrawiam 1 Cytuj Link do komentarza Share on other sites More sharing options...
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