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STM32F0 problem z obsługą nrf24l01+

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Witam, podłączyłem do mojej płytki 2 moduły nrf odpowiednio odbiornik do SPI1 a nadajnik na SPI2. Niestety mam problem z obsługą tych układów, nie zgłaszają mi one przerwań na pinach który ustawiłem jako wejściowy z pull-up oraz triggerem reagującym na zbocze opadające (sprawdzałem piny zwierając je do masy przerwanie zostało wywołane poprawnie). Funkcje obsługi SPI działają poprawnie, sprawdzałem ich działanie wpisując do rejestru nrf-a wartość a następnie ją odczytując. Wszystko działało poprawnie. Sprawdzałem również poprawność ustawień timera 2, który co ok sekundę miał posyłać dane z 1 nrf-a do 2 podłączonego. Przerwanie zostało wywołane poprawnie (sprawdzane dodatkowo miganiem diody). Niestety brak poprawnego przesłania danych. W pętli głównej sprawdzam stan rejestru status obu układów. Układ nadawczy ma ustawiony bit MAX_RT co oznacza niepowodzenie, układ odbiorczy nie ma ustawionego RX_DR bitu co oznacza brak danych. Mój kod obsługi:


#include <stm32f0xx_gpio.h>
#include <stm32f0xx_rcc.h>
#include <stm32f0xx_tim.h>
#include <stm32f0xx_misc.h>
#include <stm32f0xx_exti.h>
#include <stm32f0xx_syscfg.h>
#include <stm32f0xx_spi.h>
#include "nRFL01p.h"

#define LED_PORT GPIOC
//#define BUTTON_PORT GPIOA

//Chip Enable Activates RX or TX mode
//SPI2 Chip Enable - PB11
#define CE2_H()   GPIO_SetBits(GPIOB, GPIO_Pin_11) //RX mode
#define CE2_L()   GPIO_ResetBits(GPIOB, GPIO_Pin_11) //TX mode

//SPI1 Chip Enable - PA3
#define CE1_H()   GPIO_SetBits(GPIOA, GPIO_Pin_3) //RX mode
#define CE1_L()   GPIO_ResetBits(GPIOA, GPIO_Pin_3) //TX mode

//SPI2 Chip Select - PB12
#define SPI2_releaseChip()  GPIO_SetBits(GPIOB, GPIO_Pin_12)
#define SPI2_selectChip()  GPIO_ResetBits(GPIOB, GPIO_Pin_12)

//SPI1 Chip Select - PA2
#define SPI1_releaseChip() GPIO_SetBits(GPIOA, GPIO_Pin_2)
#define SPI1_selectChip() GPIO_ResetBits(GPIOA, GPIO_Pin_2)



//#define BAUD 250000
#define RF_PAYLOAD_LENGTH	1
#define RF_CHANNEL 120

uint8_t address_tx[] = { 0xCE, 0xCE, 0xF1, 0xF3, 0xF4 };	//LSB byte first, TX_ADDR in PTX, RX_ADDR_0 in PRX
//uint8_t address_rx[]={0x64,0x64,0xF2};	//LSB byte first, TX_ADDR in PRX, RX_ADDR_0 in PTX
uint8_t databuffer[32] = { 'H', 'E', 'L', 'L', 'O' }; 	//max size one payload in nrf24l01p
uint8_t databufferrec[32];

void Delay(uint32_t delay)
{
int i;
for (i = 0; i < delay; i++)
	asm("nop");
}

void SpiInit()
{
SPI_InitTypeDef   SPI_InitStructure;
GPIO_InitTypeDef  GPIO_InitStructure;

//SPI clk
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); //enable spi1 clk
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); //enable spi2 clk

//SCK MOSI MISO - SPI2 PB13, PB14, PB15
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; 
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);

//SCK MOSI MISO - SPI1 PA5, PA6, PA7
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7; 
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);

//SPI2 CSN - PB12
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure); 

//SPI1 CSN - PA2
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure); 

//SPI2 CE - PB11
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);

//SPI1 CE - PA3
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);

SPI_Cmd(SPI1, DISABLE); 
SPI_Cmd(SPI2, DISABLE); 

/* SPI2,1 configuration */
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; //SPI 2 lines fulldupex
SPI_InitStructure.SPI_Mode = SPI_Mode_Master; //SPI Mode master
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; //8 bit
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;   //
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; //
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;//
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; //First MSB
SPI_InitStructure.SPI_CRCPolynomial = 7; //CRC FRAME
SPI_Init(SPI2, &SPI_InitStructure);
SPI_Init(SPI1, &SPI_InitStructure);
/* Enable SPI2,1   */

SPI_Cmd(SPI1, ENABLE);
SPI_Cmd(SPI2, ENABLE);  

}

char SPI_MasterTransmit(char cData, SPI_TypeDef* SPIx)
{
while (SPI_I2S_GetFlagStatus(SPIx, SPI_I2S_FLAG_TXE) == RESET);

/* Send byte through the SPI peripheral */
SPI_SendData8(SPIx, cData);

//while (SPI_I2S_GetFlagStatus(SPIx, SPI_I2S_FLAG_RXNE) == RESET);

return SPI_ReceiveData8(SPIx);
}

uint8_t nrf_read_register(uint8_t reg, SPI_TypeDef* SPIx)
{
uint8_t tmp;

if (SPIx == SPI2)

	SPI2_selectChip(); //CSN - low

else if (SPIx == SPI1)

	SPI1_selectChip(); //CSN - low

SPI_MasterTransmit(reg, SPIx); //select register

tmp = SPI_MasterTransmit(0, SPIx); //send dummy bytes to read data

if (SPIx == SPI2)

	SPI2_releaseChip(); //CSN - high

else if (SPIx == SPI1)

	SPI1_releaseChip(); //CSN - high

return tmp;
}

uint8_t nrf_write_register(uint8_t reg, uint8_t value, SPI_TypeDef* SPIx)
{
uint8_t tmp;

if (SPIx == SPI2)

	SPI2_selectChip(); //CSN - low

else if (SPIx == SPI1)

	SPI1_selectChip(); //CSN - low


tmp = SPI_MasterTransmit(WRITE_REG | reg, SPIx);

if (reg != NOP && reg != FLUSH_TX && reg != FLUSH_RX && reg != REUSE_TX_PL)
	SPI_MasterTransmit(value, SPIx);

if (SPIx == SPI2)

	SPI2_releaseChip(); //CSN - high

else if (SPIx == SPI1)

	SPI1_releaseChip(); //CSN - high


return tmp;
}

uint16_t nrf_read_multibyte_register(uint8_t reg, uint8_t *pbuf, SPI_TypeDef* SPIx)
{
uint8_t ctr, length;
switch (reg)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_TX:

	length = ctr = (nrf_read_register(SETUP_AW, SPIx) + 2); //RX/TX Address field width
	if (SPIx == SPI2)

		SPI2_selectChip(); //CSN - low

	else if (SPIx == SPI1)

		SPI1_selectChip(); //CSN - low

	SPI_MasterTransmit(RX_ADDR_P0 + reg, SPIx);
	break;

case HAL_NRF_RX_PLOAD:
	if ((reg = ((nrf_write_register(NOP, 0, SPIx) & 0x0E) >> 1)) < 7)
	{	//read Data pipe number for the payload available for reading from  RX_FIFO
		length = ctr = nrf_read_register(RD_RX_PLOAD_W, SPIx);

		if (SPIx == SPI2)

			SPI2_selectChip(); //CSN - low

		else if (SPIx == SPI1)

			SPI1_selectChip(); //CSN - low

		SPI_MasterTransmit(RD_RX_PLOAD, SPIx);
	}
	else ctr = length = 0;
	break;

default:
	ctr = length = 0;
	break;
}

while (ctr--) *pbuf++ = SPI_MasterTransmit(0, SPIx);

if (SPIx == SPI2)

	SPI2_releaseChip(); //CSN - high

else if (SPIx == SPI1)

	SPI1_releaseChip(); //CSN - high


return (((uint16_t) reg << 8) | length);
}


void nrf_write_multibyte_reg(uint8_t reg, uint8_t *pbuf, uint8_t length, uint8_t pipe, SPI_TypeDef* SPIx)
{
switch (reg)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_TX:
	length = (nrf_read_register(SETUP_AW, SPIx) + 2); //RX/TX Address field width
	if (SPIx == SPI2)

		SPI2_selectChip(); //CSN - low

	else if (SPIx == SPI1)

		SPI1_selectChip(); //CSN - low

	SPI_MasterTransmit(WRITE_REG + RX_ADDR_P0 + reg, SPIx);
	break;

case HAL_NRF_TX_PLOAD:
	if (SPIx == SPI2)

		SPI2_selectChip(); //CSN - low

	else if (SPIx == SPI1)

		SPI1_selectChip(); //CSN - low

	SPI_MasterTransmit(WR_TX_PLOAD, SPIx);
	break;

case HAL_NRF_ACK_PLOAD:
	if (SPIx == SPI2)

		SPI2_selectChip(); //CSN - low

	else if (SPIx == SPI1)

		SPI1_selectChip(); //CSN - low

	SPI_MasterTransmit(WR_ACK_PLOAD | pipe, SPIx);
	break;

case HAL_NRF_TX_PLOAD_NOACK:
	if (SPIx == SPI2)

		SPI2_selectChip(); //CSN - low

	else if (SPIx == SPI1)

		SPI1_selectChip(); //CSN - low

	SPI_MasterTransmit(WR_NAC_TX_PLOAD, SPIx);
	break;

default:
	break;
}

while (length--) SPI_MasterTransmit(*pbuf++, SPIx);

if (SPIx == SPI2)

	SPI2_releaseChip(); //CSN - high

else if (SPIx == SPI1)

	SPI1_releaseChip(); //CSN - high

}

void nrfRecieverInit(SPI_TypeDef* SPIx)
{
uint8_t status = 0;
//Delay(150000);
nrf_write_register(SETUP_AW, 1, SPIx);	//address field width = 3 bytes (see size address_Xx tables)
status = nrf_read_register(SETUP_AW, SPIx); //1 jest 3
nrf_write_register(SETUP_RETR, ARD_1500US | ARC_3, SPIx);	//auto retransmit delay=1500us (250kbps), auto retransmit count=3
status = nrf_read_register(SETUP_RETR, SPIx); //83
nrf_write_register(RF_CH, RF_CHANNEL, SPIx);	// frequency channel=2400 + RF_CHANNEL MHz 120
status = nrf_read_register(RF_CH, SPIx); //120
nrf_write_register(RF_SETUP, 1 << RF_DR_LOW | HAL_NRF_0DBM << 1, SPIx);	//data rate=250kbps, power=0dBm
status = nrf_read_register(RF_SETUP, SPIx); //38
nrf_write_multibyte_reg(HAL_NRF_PIPE0, address_tx, 0, 0, SPIx);	//write RX_ADDR_P0 in PRX device
//nrf_read_multibyte_register(HAL_NRF_PIPE0, databufferrec, SPIx);
nrf_write_multibyte_reg(HAL_NRF_TX, address_tx, 0, 0, SPIx);	//write TX_ADDR in PRX device
//nrf_read_multibyte_register(HAL_NRF_TX, databufferrec, SPIx);
nrf_write_register(RX_PW_P0, 32, SPIx);	//32 bytes RX payload - probably not needed in dynamic payload length ////////////////////////////////////// TODO: test comment this line
status = nrf_read_register(RX_PW_P0, SPIx); //32
nrf_write_register(FEATURE, 1 << EN_DPL | 1 << EN_ACK_PAY, SPIx);	//enable Dynamic Payload Length and Payload with ACK feature
status = nrf_read_register(FEATURE, SPIx);//6
nrf_write_register(DYNPD, 1 << DPL_P0, SPIx);	//Enable dynamic payload length data pipe 0 (Requires  EN_DPL  and  ENAA_P0 )
status = nrf_read_register(DYNPD, SPIx);// 1
nrf_write_register(CONFIG, 1 << EN_CRC | 1 << PRIM_RX | 1 << PWR_UP, SPIx);	//PRX mode, power UP
status = nrf_read_register(CONFIG, SPIx);
Delay(5000);
CE1_H(); //RX mode
Delay(1000);	
}

void nrfTransmiterInit(SPI_TypeDef* SPIx)
{
uint8_t status = 0;
Delay(150000);//Power on reset=100ms (little more, depends on circuit and voltage regulator)

nrf_write_register(SETUP_AW, 1, SPIx);	//address field width = 3 bytes (see size address_Xx tables) 1
status = nrf_read_register(SETUP_AW, SPIx); //1 jest 1
nrf_write_register(SETUP_RETR, ARD_1500US | ARC_3, SPIx);	//auto retransmit delay=1500us (250kbps), auto retransmit count=3
status = nrf_read_register(SETUP_RETR, SPIx); //83
nrf_write_register(RF_CH, RF_CHANNEL, SPIx);	// frequency channel=2400 + RF_CHANNEL MHz
status = nrf_read_register(RF_CH, SPIx);//120
nrf_write_register(RF_SETUP, 1 << RF_DR_LOW | HAL_NRF_0DBM << 1, SPIx);	//data rate=250kbps, power=0dBm
status = nrf_read_register(RF_SETUP, SPIx);//38
nrf_write_multibyte_reg(HAL_NRF_PIPE0, address_tx, sizeof address_tx, 0, SPIx);	//write RX_ADDR_P0 in PTX device
//nrf_read_multibyte_register(HAL_NRF_PIPE0, databufferrec, SPIx);
nrf_write_multibyte_reg(HAL_NRF_TX, address_tx, sizeof address_tx, 0, SPIx);	//write TX_ADDR in PTX device
//nrf_read_multibyte_register(HAL_NRF_TX, databufferrec, SPIx);
nrf_write_register(RX_PW_P0, 32, SPIx);	//32 bytes RX payload - probably not needed in dynamic payload length
status = nrf_read_register(RX_PW_P0, SPIx); //32
nrf_write_register(FEATURE, 1 << EN_DPL | 1 << EN_ACK_PAY, SPIx);	//enable Dynamic Payload Length and Payload with ACK feature
status = nrf_read_register(FEATURE, SPIx);//6
nrf_write_register(DYNPD, 1 << DPL_P0, SPIx);	//Enable dynamic payload length data pipe 0 (Requires  EN_DPL  and  ENAA_P0 )
status = nrf_read_register(DYNPD, SPIx);//1
nrf_write_register(CONFIG, 1 << EN_CRC | 1 << PWR_UP, SPIx);	//PTX mode, power UP
Delay(5000);	//wait Tpd2stby
status = nrf_read_register(CONFIG, SPIx);
CE2_L(); //TX Mode
Delay(1000);
}

void InitializeTimer()
{
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);

TIM_TimeBaseInitTypeDef timerInitStructure;
timerInitStructure.TIM_Prescaler = 48000;
timerInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
timerInitStructure.TIM_Period = 1000;
timerInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
timerInitStructure.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM2, &timerInitStructure);
TIM_Cmd(TIM2, ENABLE);
TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
////TIMER1 init 
//RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
//
//TIM_TimeBaseInitTypeDef timerInitStructure;
//timerInitStructure.TIM_Prescaler = 48000;
//timerInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
//timerInitStructure.TIM_Period = 1000;
//timerInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
//timerInitStructure.TIM_RepetitionCounter = 0;
//TIM_TimeBaseInit(TIM1, &timerInitStructure);
//TIM_Cmd(TIM1, ENABLE);
//TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);

////TIMER interrupt init
//NVIC_InitTypeDef nvicStructure;
//nvicStructure.NVIC_IRQChannel = TIM14_IRQn;
//nvicStructure.NVIC_IRQChannelPriority = 0;
//nvicStructure.NVIC_IRQChannelCmd = ENABLE;
//NVIC_Init(&nvicStructure);
}

void EnableTimerInterrupt()
{
NVIC_InitTypeDef nvicStructure;
nvicStructure.NVIC_IRQChannel = TIM2_IRQn;
nvicStructure.NVIC_IRQChannelPriority = 0;
nvicStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&nvicStructure);
}

void EnableButtonWihoutInterrupt()
{
GPIO_InitTypeDef GPIO_InitStructure;
//usr button PA0
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; //rezystor pull down
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStructure);
}


void EnableButtonInterrupt()
{
GPIO_InitTypeDef GPIO_InitStructure;
//usr button PA0, PA1
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
//GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStructure);

//NVIC config channel 0-1, priority 0
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = EXTI0_1_IRQn;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_InitStructure.NVIC_IRQChannelPriority = 0;
NVIC_Init(&NVIC_InitStructure);

//interrupt source - PA0 
SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA,EXTI_PinSource0);

//EXTI config - interrupt on LINE0
EXTI_InitTypeDef EXTI_InitStruct;
EXTI_InitStruct.EXTI_Line = EXTI_Line0;
EXTI_InitStruct.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStruct);

//interrupt source - PA1
SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource1);

//EXTI config - interrupt on LINE1
EXTI_InitStruct.EXTI_Line = EXTI_Line1;
EXTI_InitStruct.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStruct);
}

void GPIO_ToggleBit(GPIO_TypeDef* PORT, uint16_t GPIO_PIN)
{
static uint16_t toggle_flag[32] = { 0 };
uint16_t pin;

switch (GPIO_PIN)
{
	case GPIO_Pin_8: pin = 8; break;
	case GPIO_Pin_9: pin = 9; break;	
}

toggle_flag[pin] ^= 1;

if (toggle_flag[pin] == 1)
{
	GPIO_WriteBit(PORT, GPIO_PIN, Bit_SET);
}
else
{
	GPIO_WriteBit(PORT, GPIO_PIN, Bit_RESET);
}
}

int main()
{
GPIO_InitTypeDef GPIO_InitStructure;

//enable GPIOC,GPIOA
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);

//LED PC9 PC8
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(LED_PORT, &GPIO_InitStructure);

SpiInit();
nrfTransmiterInit(SPI2);
nrfRecieverInit(SPI1);
InitializeTimer();
EnableTimerInterrupt();
EnableButtonInterrupt();

uint8_t status = 0;

for (;;)
{
	status = nrf_read_register(STATUS, SPI1);
	status = nrf_read_register(STATUS, SPI2);

}
}

//TIMER 2 interrupt
extern "C" void TIM2_IRQHandler()
{
if (TIM_GetITStatus(TIM2, TIM_IT_Update) != RESET)
{
	TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
	GPIO_ToggleBit(LED_PORT, GPIO_Pin_8);
	nrf_write_multibyte_reg(HAL_NRF_TX_PLOAD, databuffer, 5, 0, SPI1);
}
}

//EXTI0
extern "C" void EXTI0_1_IRQHandler()
{
//if interrupt is from LINE0
if (EXTI_GetITStatus(EXTI_Line0) != RESET)
{
	GPIO_ToggleBit(LED_PORT, GPIO_Pin_9);

	switch ((nrf_write_register(STATUS, 1 << MAX_RT | 1 << TX_DS | 1 << RX_DR, SPI1)) & (1 << MAX_RT | 1 << TX_DS | 1 << RX_DR))	//read status register and clear interrupt flags
	{
	case (1 << HAL_NRF_MAX_RT):					// Max retries reached
		nrf_write_register(FLUSH_TX, 0, SPI1);	// flush tx fifo, avoid fifo jam
			//uart_putc(0x01);
		break;

	case (1 << HAL_NRF_TX_DS):                  // Packet sent
		//nrf_write_register(FLUSH_RX,0);
			//uart_putc(0x02);
		break;

	case (1 << HAL_NRF_RX_DR):                  // Packet received
		while (!((nrf_write_register(NOP, 0, SPI1) & 0x0E) == 0x0E))	//while RF FIFO is not Empty RX_P_NO != 111		
			nrf_read_multibyte_register(HAL_NRF_RX_PLOAD, databufferrec,SPI1);	//read payload data	
			//uart_putc(0x03);
		break;

	case ((1 << HAL_NRF_RX_DR) | (1 << HAL_NRF_TX_DS)): // Ack payload recieved
		while (!((nrf_write_register(NOP, 0, SPI1) & 0x0E) == 0x0E))	//while RF FIFO is not Empty RX_P_NO != 111	
			nrf_read_multibyte_register(HAL_NRF_RX_PLOAD, databuffer, SPI1);	//read payload ACK data			
			//uart_putc(0x04);
		break;

	default:
		while (!((nrf_write_register(NOP, 0, SPI1) & 0x0E) == 0x0E))	//while RF FIFO is not Empty RX_P_NO != 111
			nrf_read_multibyte_register(HAL_NRF_RX_PLOAD, databuffer, SPI1);	//read payload data
		break;	
	}
	//clear interrupt bit
	EXTI_ClearITPendingBit(EXTI_Line0); 
}
//if interrupt is from LINE1
if (EXTI_GetITStatus(EXTI_Line1) != RESET)
{
	GPIO_ToggleBit(LED_PORT, GPIO_Pin_9);
	//clear interrupt bit
	EXTI_ClearITPendingBit(EXTI_Line1);
}
}

Oraz plik nagłówkowy:



/*
* nRF24L01p.h
*
* Created: 2015-04-11 13:50:17
*  Author: Michał
*/ 


#ifndef NRF24L01P_H_
#define NRF24L01P_H_

/* Copyright (c) 2006 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is confidential property of Nordic Semiconductor. The use,
* copying, transfer or disclosure of such information is prohibited except by express written
* agreement with Nordic Semiconductor.
*
* $Rev: 1731 $
*
*/

/** @file
* Register definitions for the nRF HAL module
* @defgroup nordic_hal_nrf_reg nRF24L01 Register definitions
* @{
* @ingroup nordic_hal_nrf
* Header file defining register mapping with bit definitions.\ This file is radio-chip dependent, and are included with the hal_nrf.h
*/


/** @name - Instruction Set - */
//@{
/* nRF24L01 Instruction Definitions */
#define WRITE_REG     0x20  /**< Register write command */
#define RD_RX_PLOAD_W   0x60  /**< Read RX width payload command */
#define RD_RX_PLOAD   0x61  /**< Read RX payload command */
#define WR_TX_PLOAD   0xA0  /**< Write TX payload command */
#define WR_ACK_PLOAD  0xA8  /**< Write ACK payload command */
#define WR_NAC_TX_PLOAD 0xB0  /**< Write ACK payload command */
#define FLUSH_TX      0xE1  /**< Flush TX register command */
#define FLUSH_RX      0xE2  /**< Flush RX register command */
#define REUSE_TX_PL   0xE3  /**< Reuse TX payload command */
#define LOCK_UNLOCK   0x50  /**< Lock/unlcok exclusive features */

#define NOP           0xFF  /**< No Operation command, used for reading status register */
//@}

/** @name  - Register Memory Map - */
//@{
/* nRF24L01 * Register Definitions * */
#define CONFIG        0x00  /**< nRF24L01 config register */
#define EN_AA         0x01  /**< nRF24L01 enable Auto-Acknowledge register */
#define EN_RXADDR     0x02  /**< nRF24L01 enable RX addresses register */
#define SETUP_AW      0x03  /**< nRF24L01 setup of address width register */
#define SETUP_RETR    0x04  /**< nRF24L01 setup of automatic retransmission register */
#define RF_CH         0x05  /**< nRF24L01 RF channel register */
#define RF_SETUP      0x06  /**< nRF24L01 RF setup register */
#define STATUS        0x07  /**< nRF24L01 status register */
#define OBSERVE_TX    0x08  /**< nRF24L01 transmit observe register */
#define CD            0x09  /**< nRF24L01 carrier detect register */
#define RX_ADDR_P0    0x0A  /**< nRF24L01 receive address data pipe0 */
#define RX_ADDR_P1    0x0B  /**< nRF24L01 receive address data pipe1 */
#define RX_ADDR_P2    0x0C  /**< nRF24L01 receive address data pipe2 */
#define RX_ADDR_P3    0x0D  /**< nRF24L01 receive address data pipe3 */
#define RX_ADDR_P4    0x0E  /**< nRF24L01 receive address data pipe4 */
#define RX_ADDR_P5    0x0F  /**< nRF24L01 receive address data pipe5 */
#define TX_ADDR       0x10  /**< nRF24L01 transmit address */
#define RX_PW_P0      0x11  /**< nRF24L01 \# of bytes in rx payload for pipe0 */
#define RX_PW_P1      0x12  /**< nRF24L01 \# of bytes in rx payload for pipe1 */
#define RX_PW_P2      0x13  /**< nRF24L01 \# of bytes in rx payload for pipe2 */
#define RX_PW_P3      0x14  /**< nRF24L01 \# of bytes in rx payload for pipe3 */
#define RX_PW_P4      0x15  /**< nRF24L01 \# of bytes in rx payload for pipe4 */
#define RX_PW_P5      0x16  /**< nRF24L01 \# of bytes in rx payload for pipe5 */
#define FIFO_STATUS   0x17  /**< nRF24L01 FIFO status register */
#define DYNPD         0x1C  /**< nRF24L01 Dynamic payload setup */
#define FEATURE       0x1D  /**< nRF24L01 Exclusive feature setup */

//@}

/* nRF24L01 related definitions */
/* Interrupt definitions */
/* Operation mode definitions */

/** An enum describing the radio's irq sources.
*
*/
typedef enum {
HAL_NRF_MAX_RT = 4,     /**< Max retries interrupt */
HAL_NRF_TX_DS,          /**< TX data sent interrupt */
HAL_NRF_RX_DR           /**< RX data received interrupt */
} hal_nrf_irq_source_t;

/* Operation mode definitions */
/** An enum describing the radio's power mode.
*
*/
typedef enum {
HAL_NRF_PTX,            /**< Primary TX operation */
HAL_NRF_PRX             /**< Primary RX operation */
} hal_nrf_operation_mode_t;

/** An enum describing the radio's power mode.
*
*/
typedef enum {
HAL_NRF_PWR_DOWN,       /**< Device power-down */
HAL_NRF_PWR_UP          /**< Device power-up */
} hal_nrf_pwr_mode_t;

/** An enum describing the radio's output power mode's.
*
*/
typedef enum {
HAL_NRF_18DBM,          /**< Output power set to -18dBm */
HAL_NRF_12DBM,          /**< Output power set to -12dBm */
HAL_NRF_6DBM,           /**< Output power set to -6dBm  */
HAL_NRF_0DBM            /**< Output power set to 0dBm   */
} hal_nrf_output_power_t;

/** An enum describing the radio's on-air datarate.
*
*/
typedef enum {
HAL_NRF_1MBPS,          /**< Datarate set to 1 Mbps  */
HAL_NRF_2MBPS           /**< Datarate set to 2 Mbps  */
} hal_nrf_datarate_t;

/** An enum describing the radio's PLL mode.
*
*/
typedef enum {
HAL_NRF_PLL_UNLOCK,     /**< PLL unlocked, normal operation  */
HAL_NRF_PLL_LOCK        /**< PLL locked, test mode  */
} hal_nrf_pll_mode_t;

/** An enum describing the radio's LNA mode.
*
*/
typedef enum {
HAL_NRF_LNA_LCURR,      /**< LNA set to low current mode */
HAL_NRF_LNA_HCURR       /**< LNA set to high current mode */
} hal_nrf_lna_mode_t;

/** An enum describing the radio's CRC mode.
*
*/
typedef enum {
HAL_NRF_CRC_OFF,        /**< CRC check disabled */
HAL_NRF_CRC_8BIT  = 2,   /**< CRC check set to 8-bit */
HAL_NRF_CRC_16BIT       /**< CRC check set to 16-bit */
} hal_nrf_crc_mode_t;

/** An enum describing the read/write payload command.
*
*/
typedef enum {
HAL_NRF_TX_PLOAD       = 7,   /**< TX payload definition */
HAL_NRF_RX_PLOAD,        /**< RX payload definition */
HAL_NRF_ACK_PLOAD,
HAL_NRF_TX_PLOAD_NOACK
} hal_nrf_pload_command_t;

/** Structure containing the radio's address map.
* Pipe0 contains 5 unique address bytes,
* while pipe[1..5] share the 4 MSB bytes, set in pipe1.
* <p><b> - Remember that the LSB byte for all pipes have to be unique! -</b>
*/
// nRF24L01 Address struct

/*
//typedef struct {
//   uint8_t p0[5];            /**< Pipe0 address, 5 bytes */
//    uint8_t p1[5];            /**< Pipe1 address, 5 bytes, 4 MSB bytes shared for pipe1 to pipe5 */
//    uint8_t p2[1];            /**< Pipe2 address, 1 byte */
//    uint8_t p3[1];            /**< Pipe3 address, 1 byte */
//   uint8_t p4[1];            /**< Pipe3 address, 1 byte */
//   uint8_t p5[1];            /**< Pipe3 address, 1 byte */
//   uint8_t tx[5];            /**< TX address, 5 byte */
//} hal_nrf_l01_addr_map;


/** An enum describing the nRF24L01 pipe addresses and TX address.
*
*/
typedef enum {
HAL_NRF_PIPE0,              /**< Select pipe0 */
HAL_NRF_PIPE1,              /**< Select pipe1 */
HAL_NRF_PIPE2,              /**< Select pipe2 */
HAL_NRF_PIPE3,              /**< Select pipe3 */
HAL_NRF_PIPE4,              /**< Select pipe4 */
HAL_NRF_PIPE5,              /**< Select pipe5 */
HAL_NRF_TX,                 /**< Refer to TX address*/
HAL_NRF_ALL   = 0xFF          /**< Close or open all pipes*/
                            /**< @see hal_nrf_set_address @see hal_nrf_get_address
                             @see hal_nrf_open_pipe  @see hal_nrf_close_pipe */
} hal_nrf_address_t;

/** An enum describing the radio's address width.
*
*/
typedef enum {
HAL_NRF_AW_3BYTES = 3,      /**< Set address width to 3 bytes */
HAL_NRF_AW_4BYTES,          /**< Set address width to 4 bytes */
HAL_NRF_AW_5BYTES           /**< Set address width to 5 bytes */
} hal_nrf_address_width_t;


/** @name CONFIG register bit definitions */
//@{

#define MASK_RX_DR    6     /**< CONFIG register bit 6 */
#define MASK_TX_DS    5     /**< CONFIG register bit 5 */
#define MASK_MAX_RT   4     /**< CONFIG register bit 4 */
#define EN_CRC        3     /**< CONFIG register bit 3 */
#define CRCO          2     /**< CONFIG register bit 2 */
#define PWR_UP        1     /**< CONFIG register bit 1 */
#define PRIM_RX       0     /**< CONFIG register bit 0 */
//@}

/** @name RF_SETUP register bit definitions */
//@{
#define RF_DR_LOW	  5		/**< RF_SETUP register bit 5 */
#define PLL_LOCK      4     /**< RF_SETUP register bit 4 */
#define RF_DR         3     /**< RF_SETUP register bit 3 */
#define RF_PWR1       2     /**< RF_SETUP register bit 2 */
#define RF_PWR0       1     /**< RF_SETUP register bit 1 */
#define LNA_HCURR     0     /**< RF_SETUP register bit 0 */
//@}

/* STATUS 0x07 */
/** @name STATUS register bit definitions */
//@{
#define RX_DR         6     /**< STATUS register bit 6 */
#define TX_DS         5     /**< STATUS register bit 5 */
#define MAX_RT        4     /**< STATUS register bit 4 */
#define TX_FULL       0     /**< STATUS register bit 0 */
//@}

/* FIFO_STATUS 0x17 */
/** @name FIFO_STATUS register bit definitions */
//@{
#define TX_REUSE      6     /**< FIFO_STATUS register bit 6 */
#define TX_FIFO_FULL  5     /**< FIFO_STATUS register bit 5 */
#define TX_EMPTY      4     /**< FIFO_STATUS register bit 4 */
#define RX_FULL       1     /**< FIFO_STATUS register bit 1 */
#define RX_EMPTY      0     /**< FIFO_STATUS register bit 0 */
//@}

#define	EN_DPL		  2
#define EN_ACK_PAY	  1
#define EN_DYN_ACK	  0

#define DPL_P5		  5
#define DPL_P4		  4
#define DPL_P3		  3
#define DPL_P2		  2
#define DPL_P1		  1
#define DPL_P0		  0

#define ARD_250US	0x00
#define ARD_500US	0x10
#define ARD_750US	0x20
#define ARD_1000us	0x30
#define ARD_1250US	0x40
#define ARD_1500US	0x50
#define ARD_1750US	0x60
#define ARD_2000US	0x70

#define ARC_DISABLE	0x00
#define ARC_1		0x01
#define ARC_2		0x02
#define ARC_3		0x03
#define ARC_4		0x04

#endif /* NRF24L01P_H_ */

Z góry dziękuję za pomoc, siedze i szukam błędu w kodzie, ale naprawdę już nie umiem go znaleźć, podejrzewam po prostu złą konfigurację w funkcjach init, oraz problem z konfiguracją linii odpowiedzialnymi za przerwanie (PA0, PA1).

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